Abstract: The present invention is directed to a method for inducing an immune response in a subject, including a step of activating neurons in the mesolimbic network of the subject by applying a neurofeedback.

Abstract: A network processor has a “bi-level” architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. Each classification algorithm engine generates one or more single-record search requests to search the hash database for classification information based on one or more field values of the received packet or other classification parameters. Each single-record search requests is provided to the single-record search level, which executes the requests at the hash database and returns the corresponding record to the requesting classification algorithm engine.

Abstract: A temporal-miss handler includes updating a data leaf in a tree-structured database of a communications processor with a plurality of threads. A search for the data leaf includes generating at least one search result for one of the plurality of threads. A sufficiency of a temporal separation, between updating the data leaf and searching for the data leaf, to retrieve the data leaf is determined. Each search result is cleared when the temporal separation is insufficient. A new search is performed when the temporal separation is insufficient.

Abstract: A data processing device includes a hash table management module that sequentially steps through linear address space of the hash table to identify hash chain in sequential address order. Each identified hash chain is evaluated, before identifying a next hash chain, to remove any entries marked for deletion.

Abstract: A network processor has a “bi-level” architecture including a classification algorithm level and a single-record search level to search a hash database that stores packet classification information based on packet field values. The classification algorithm level implements multiple different classification algorithm engines, wherein the individual algorithm applied to a received packet can be selected based on a field of the packet, a port at which the packet was received, or other criteria. Each classification algorithm engine generates one or more single-record search requests to search the hash database for classification information based on one or more field values of the received packet or other classification parameters. Each single-record search requests is provided to the single-record search level, which executes the requests at the hash database and returns the corresponding record to the requesting classification algorithm engine.

Abstract: A data processing device includes a hash table management module that sequentially steps through linear address space of the hash table to identify hash chain in sequential address order. Each identified hash chain is evaluated, before identifying a next hash chain, to remove any entries marked for deletion.

Abstract: A temporal-miss handler includes updating a data leaf in a tree-structured database of a communications processor with a plurality of threads. A search for the data leaf includes generating at least one search result for one of the plurality of threads. A sufficiency of a temporal separation, between updating the data leaf and searching for the data leaf, to retrieve the data leaf is determined. Each search result is cleared when the temporal separation is insufficient. A new search is performed when the temporal separation is insufficient.

Abstract: A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.

Abstract: A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate.

Abstract: A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages.

Abstract: A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.

Abstract: A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate.

Abstract: A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages.