Abstract: An integrated circuit device comprising one or more data processing circuits, each having an input stage, a combinatorial logic stage and an output stage. The input stage is responsive to a clock signal, and receives at least a first and second set of data signals and provides the first set to an input of the logic stage during a first portion of a clock signal period, and provides the second set to the input during a second portion of the period. The output stage is responsive to the clock signal, and receives from an output of the logic stage at least a first result signal as a function of the first set during a first portion of a subsequent clock signal period and receives from the output at least a second result signal as a function of the second set during a second portion of the subsequent period.

Abstract: An integrated circuit device comprising one or more data processing circuits is provided, where each data processing circuit has an input stage, a combinatorial logic stage and an output stage. The input stage is responsive to a clock signal, and receives at least a first and a second set of data signals and provides the first set of data signals to an input of the combinatorial logic stage during a first portion of a period of the clock signal, and provides the second set of data signals to the input during a second portion of the period. The output stage is responsive to the clock signal, and receives from an output of the combinatorial logic stage at least a first result signal as a function of the first set of data signals during a first portion of a subsequent period of the clock signal and receive from the output at least a second result signal as a function of the second set of data signals during a second portion of the subsequent period.

Abstract: A method and apparatus are provided for inserting an address at the beginning of a data stream that is being transferred through a FIFO buffer (65). The address is inserted at the beginning of the data stream to prevent the address from being lost. An address decoder (102) is used to identify a range of addresses that can access the FIFO buffer (65). The address may also contain header information for determining the destination of the data stream in a data processing system (20), and also contain information for controlling how the data stream is to be processed in the data processing system (20).

Abstract: An adjustable depth/width FIFO buffer (65) is provided that accommodates variable width data transfers. The FIFO buffer (65) has two sections of read/write registers (73, 75) that are each independently controlled for transferring 16 bit words or 32 bit words without wasting register space in the FIFO buffer (65) when transferring 16 bit words. When the FIFO buffer (65) is narrowed to transfer 16 bit words, the storage space is deepened. This allows maximum use of the FIFO buffer registers (72) when interfacing either 16 bits of parallel data or 32 bits of parallel data. The FIFO buffer (65) is a slave only buffer to a host processor, therefore, the FIFO buffer (65) cannot initiate output of data, keeping the design simple and small.