Abstract: A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length decoding independently of the other length decoders in the instruction marking circuit. A length decoder determines whether a byte being processed is a prefix byte to an instruction. If a length-affecting prefix byte is found, the length decoder signals a subsequent length decoder to indicate that a prefix byte has been found. The subsequent length decoder uses the prefix signal to appropriately length decode the byte being processed by the subsequent length decoder. Signals are provided to continue the self-timed marking process. Prefix handling may also be used in a multiple marking unit configuration of an instruction marking circuit.

Abstract: A self-timed instruction marking circuit includes a long instruction processing system to divide long instruction processing between two columns of the instruction marking circuit. Length decoders are interconnected across columns to signal the presence and length of long instructions. Self-timed marking can continue without alteration. The number of connections required by the instruction marking circuit are reduced. The marking process can be optimized to efficiently process all instructions by setting the definition of a long instruction such that commonly executed instructions are not included.

Abstract: An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling logic is provided in an instruction marking circuit to directly mark a target instruction of a predicted branch as the next instruction to be decoded. Additionally, a branch target FIFO may be used to store information about the location of the target instruction in the instruction stream.

Abstract: A processor and method implemented in a processor, having a pipeline and trap generation capabilities, for indicating a pipelined instruction and for generating a trap upon modification of the pipeline. Improved trap handling capabilities and improved overall system performance is provided by reducing unnecessary saving and restoring of the pipeline during certain trap handling procedures, such as those that do not modify the state of the pipeline.

Abstract: Methods and apparatus for formal verification. In one embodiment, values within a full model for formal verification are parameterized so that the parameters may be defined in order to perform verification on a reduced model. The number of states may then be reduced to allow formal verification on portions of a logic model of complex circuits such as microprocessors using present formal verification techniques. Preprocessor directives are used for multiple and conditional hardware description language generation for representation of a logic model of an integrated circuit, such as a microprocessor. Signals may also be freed from their associated circuitry, and placed into a non-deterministic state. Signals may also be set to a deterministic, designer-specified value. Associated circuitry may then be removed from the logic model for verification of a reduced model.

Abstract: A translation look-aside buffer is implemented utilizing a four-way set associative cache memory having four lines of 16 sets each. A virtual address tag and its corresponding physical address tag, as well as a number of status bits which control the type of access permitted for a given virtual address, are stored in the translation look-aside buffer. A portion of the inputted virtual address signal is used to provide a virtual address tag and is compared to the virtual address tag in the buffer memory. When the virtual address tag comparison is achieved, the physical address tags are provided as an output from the translation look-aside buffer. Also at the same time, a fault detection circuit performs various fault detection logic on the status bits, depending on the execution cycle being performed, such as read/write cycle or user/supervisor mode.