Patents by Inventor Shail Aditya Gupta

Shail Aditya Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10891132
    Abstract: For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Rishi Surendran
  • Patent number: 10891414
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Srinivas Beeravolu, Dinesh K. Monga, Pradip Jha, Vishal Suthar, Vinod K. Kathail, Vidhumouli Hunsigida, Siddarth Rele
  • Patent number: 10872057
    Abstract: An example method of placing kernels of an application in a data processing engine array (DPE) of a system on chip (SOC) includes obtaining a graph of the application having nodes representing the kernels and edges representing communication between the kernels, sorting the kernels based on runtime ratio associated with each of the kernels, processing the sorted kernels sequentially to place into partitions, determining an execution order of kernels in each of the partitions; and generating implementation data for the SOC for implementing the application therein based on the determined partitions and execution order for each of the partitions.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 22, 2020
    Assignee: XILINX, INC.
    Inventors: Prashant S. Rawat, Shail Aditya Gupta
  • Patent number: 10860766
    Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: December 8, 2020
    Assignee: XILINX, INC.
    Inventors: Mukund Sivaraman, Shail Aditya Gupta, Akella Sastry, Rishi Surendran, Philip B. James-Roxby, Samuel R. Bayliss, Vinod K. Kathail, Ajit K. Agarwal, Ralph D. Wittig
  • Publication number: 20200371759
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Akella Sastry, Vinod K. Kathail, L. James Hwang, Shail Aditya Gupta, Vidhumouli Hunsigida, Siddarth Rele
  • Publication number: 20200372123
    Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Srinivas Beeravolu, Dinesh K. Monga, Pradip Jha, Vishal Suthar, Vinod K. Kathail, Vidhumouli Hunsigida, Siddarth Rele
  • Publication number: 20200371761
    Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Samuel R. Bayliss, Vinod K. Kathail, Ralph D. Wittig, Philip B. James-Roxby, Akella Sastry
  • Publication number: 20200372200
    Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Mukund Sivaraman, Shail Aditya Gupta, Akella Sastry, Rishi Surendran, Philip B. James-Roxby, Samuel R. Bayliss, Vinod K. Kathail, Ajit K. Agarwal, Ralph D. Wittig
  • Publication number: 20200371787
    Abstract: For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.
    Type: Application
    Filed: May 23, 2019
    Publication date: November 26, 2020
    Applicant: Xilinx, Inc.
    Inventors: Shail Aditya Gupta, Rishi Surendran
  • Patent number: 10802807
    Abstract: Embodiments herein use control application programming interfaces (APIs) to control the execution of a dataflow graph in a heterogeneous processing system. That is, embodiments herein describe a programming model along with associated APIs and methods that can control, interact, and at least partially reconfigure a user application (e.g., the dataflow graph) executing on the heterogeneous processing system through a local executing control program. Using the control APIs, users can manipulate such remotely executing graphs directly as local objects and perform control operations on them (e.g., for loading and initializing the graphs; dynamically adjusting parameters for adaptive control; monitoring application parameters, system states and events; scheduling operations to read and write data across the distributed memory boundary of the platform; controlling the execution life-cycle of a subsystem; and partially reconfiguring the computing resources for a new subsystem).
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: October 13, 2020
    Assignee: XILINX, INC.
    Inventors: Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Philip B. James-Roxby, Ralph D. Wittig, Vinod Kathail
  • Patent number: 10628622
    Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes obtaining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding at least one first-in-first-out (FIFO) buffer to at least one of the communication channels, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 21, 2020
    Assignee: XILINX, INC.
    Inventors: Mukund Sivaraman, Shail Aditya Gupta, Abnikant Singh
  • Patent number: 9680893
    Abstract: Method, system, and programs for event state management in stream processing. In one example, a batch of events is created from a plurality of input events. The batch is associated with a state and is to be processed in one or more stages. The batch of events is stored in a persistent storage. The state associated with the batch is updated based on results of processing the batch in the one or more stages. The state associated with the batch is retrieved.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: June 13, 2017
    Assignee: EXCALIBUR IP, LLC
    Inventors: Joy Banerjee, Shail Aditya Gupta
  • Publication number: 20140280766
    Abstract: Method, system, and programs for event state management in stream processing. In one example, a batch of events is created from a plurality of input events. The batch is associated with a state and is to be processed in one or more stages. The batch of events is stored in a persistent storage. The state associated with the batch is updated based on results of processing the batch in the one or more stages. The state associated with the batch is retrieved.
    Type: Application
    Filed: June 19, 2013
    Publication date: September 18, 2014
    Inventors: Joy Banerjee, Shail Aditya Gupta
  • Patent number: 7484079
    Abstract: An embodiment of the present invention includes a pipeline comprising a plurality of stages and a pipeline timing controller controlling a plurality of predetermined delays, wherein, when one of the predetermined delays has expired, the pipeline timing controller sends a control signal to initiate at least one process within associated ones of the plurality of stages.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: January 27, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Shail Aditya Gupta, Mukund Sivaraman
  • Publication number: 20080082707
    Abstract: A method and apparatus is disclosed herein for a bus controller that supports a flexible bus protocol that handles pipelined, variable latency bus transactions while maintaining point-to-point (P2P) FIFO ordering of transactions in a non-blocking manner. In one embodiment, the apparatus includes a bus controller to receive a plurality of bus transactions at a first incoming port from a bus. The bus controller is configured to process the plurality of bus transactions in a pipelined manner, maintaining P2P FIFO ordering of the plurality of bus transactions even when the plurality of bus transactions take a variable number of cycles to complete.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 3, 2008
    Inventors: Shail Aditya Gupta, David John Simpson
  • Patent number: 7107199
    Abstract: A method of designing a pipeline comprises the steps of: accepting a task procedure expressed in a standard programming language, the task procedure including a sequence of computational steps; accepting a performance requirement of the pipeline; and automatically creating a hardware description of the pipeline, the pipeline comprising a plurality of interconnected processor stages, each of the processor stages for performing a respective one of the computational steps, the pipeline having characteristics consistent with the performance requirement of the pipeline.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: September 12, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert S. Schreiber, Shail Aditya Gupta, Vinod K. Kathail, Santosh George Abraham, Bantwal Ramakrishna Rau
  • Patent number: 7096438
    Abstract: A method for determining validity of a proposed loop iteration schedule comprising the steps of receiving a dependence graph including operations and edges between said operations; receiving a performance specification; receiving an assignment of latencies to operations of said dependence graph; and determining existence of a placement of clock cycle-boundaries in said dependence graph such that all dependence and timing constraints are satisfied for the performance specification.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: August 22, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mukund Sivaraman, Shail Aditya Gupta
  • Patent number: 7000137
    Abstract: A method for performing a global timing analysis of a proposed digital circuit comprising receiving timing models and the proposed digital circuit; determining at least one mode of circuit operation of the proposed digital circuit; deriving a sub-circuit corresponding to each of at least one mode of circuit operation; performing timing analysis on each of the sub-circuits derived corresponding to each of the modes; and combining the timing analysis results for all of the modes to determine an overall maximum circuit delay.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: February 14, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mukund Sivaraman, Shail Aditya Gupta
  • Patent number: 6966043
    Abstract: A method of considering circuit timing requirements during the circuit design process, comprising receiving a clock cycle-time constraint; receiving delay characteristics of hardware resources from a macrocell library; receiving an operation, an alternative clock cycle associated with said operation and an alternative hardware resource associated with said operation; and determining validity of the received alternative with respect to timing constraints using a hardware structural representation of the program graph.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: November 15, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Mukund Sivaraman, Shail Aditya Gupta
  • Patent number: 6952816
    Abstract: A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for generating a circuit design from a functional specification according to at least one design objective. An intermediate representation of the functional specification is formed. The intermediate representation is analyzed for identifying a physical instantiation that will possibly result in unacceptable interconnect delay or congestion. Functional units are allocated from among a plurality of candidate functional units for performing operations of the intermediate representation. Operations are scheduled to occur at specified times on said selected functional units. An architectural representation of the circuit design is formed according to results of scheduling.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: October 4, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Shail Aditya Gupta, Anita B. Rau, Mukund Sivaraman, Darren C. Conquist, Robert S. Schreiber, Michael S. Schlansker, Bantwal Ramakrishna Rau