Patents by Inventor Shail Dave

Shail Dave has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134769
    Abstract: A system applies bottleneck analysis for design and optimization of computing systems. In particular, the system constructs a bottleneck model, including a bottleneck cost graph for a workload or a function, through which factors corresponding to the execution costs of an arbitrary processor can be modeled. By using the bottleneck analysis, the system can determine bottleneck factors for an obtained cost value (e.g., time taken by an application's execution on a processor) and can reason about obtained high cost. The system determines and uses information about parameters impacting bottlenecks for execution costs and their approximate relationship with the bottlenecks to produce an optimized hardware-software configuration for execution of one or more workloads. Systematic, bottleneck-guided analysis and optimization can introduce explainability in the design and optimization process and can achieve more efficient design configurations much faster.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 25, 2024
    Inventors: Shail Dave, Aviral Shrivastava, Tony Nowatzki
  • Publication number: 20200133672
    Abstract: A coarse-grained reconfigurable array includes a processing element array, instruction memory circuitry, data memory circuitry, and an instruction fetch unit. The processing element array includes a number of processing elements. The instruction memory circuitry is coupled to the processing element array and configured to store a set of instructions. During each one of a number of processing cycles, the instruction memory circuitry provides instructions from the set of instructions to the processing elements. The instruction fetch unit is coupled to the processing element array and the instruction memory circuitry and configured to receive a result of a conditional instruction evaluated by one of the processing elements and provide the instruction fetch signals based at least in part on the result of the conditional instruction such that only instructions associated with a correct branch of the conditional instruction are provided to the plurality of processing elements.
    Type: Application
    Filed: October 26, 2018
    Publication date: April 30, 2020
    Inventors: Mahesh Balasubramanian, Shail Dave, Aviral Shrivastava, Reiley Jeyapaul
  • Patent number: 10104618
    Abstract: Saving power in a mobile terminal includes determining alignment processing moments after the mobile terminal enters a standby mode. Alignable wakeup events, which occur during alignment processing periods corresponding to each alignment processing moment, are thus controlled to commence related processing at each of the alignment processing moments. Power consumption caused by various wakeup events in a standby mode may thus be reduced and battery life of the mobile terminal may thus be improved.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: October 16, 2018
    Assignee: Nvidia Corporation
    Inventors: Li Lin, Jiukai Ma, Haonong Yu, Jun Qiu, Liangchuan Mi, Shail Dave, Zhichao Zu, Karthik Samynathan, Richard Clark
  • Publication number: 20170135043
    Abstract: Saving power in a mobile terminal includes determining alignment processing moments after the mobile terminal enters a standby mode. Alignable wakeup events, which occur during alignment processing periods corresponding to each alignment processing moment, are thus controlled to commence related processing at each of the alignment processing moments. Power consumption caused by various wakeup events in a standby mode may thus be reduced and battery life of the mobile terminal may thus be improved.
    Type: Application
    Filed: October 18, 2016
    Publication date: May 11, 2017
    Inventors: Li LIN, Jiukai MA, Haonong YU, Jun QIU, Liangchuan MI, Shail DAVE, Zhichao ZU, Karthik SAMYNATHAN, Richard CLARK
  • Patent number: 9474022
    Abstract: Saving power in a mobile terminal includes determining alignment processing moments after the mobile terminal enters a standby mode. Alignable wakeup events, which occur during alignment processing periods corresponding to each alignment processing moment, are thus controlled to commence related processing at each of the alignment processing moments. Power consumption caused by various wakeup events in a standby mode may thus be reduced and battery life of the mobile terminal may thus be improved.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: October 18, 2016
    Assignee: NVIDIA Corporation
    Inventors: Li Lin, Jiukai Ma, Haonong Yu, Jun Qiu, Liangchuan Mi, Shail Dave, Zhichao Zu, Karthik Samynathan, Richard Clark
  • Publication number: 20140221054
    Abstract: Saving power in a mobile terminal includes determining alignment processing moments after the mobile terminal enters a standby mode. Alignable wakeup events, which occur during alignment processing periods corresponding to each alignment processing moment, are thus controlled to commence related processing at each of the alignment processing moments. Power consumption caused by various wakeup events in a standby mode may thus be reduced and battery life of the mobile terminal may thus be improved.
    Type: Application
    Filed: December 2, 2013
    Publication date: August 7, 2014
    Applicant: Nvidia Corporation
    Inventors: Li LIN, Jiukai MA, Haonong YU, Jun QIU, Liangchuan MI, Shail DAVE, Zhichao ZU, Karthik SAMYNATHAN, Richard CLARK
  • Patent number: 8031198
    Abstract: An apparatus and method for servicing multiple graphics processing channels are described. In one embodiment, a graphics processing apparatus includes a scheduler configured to direct servicing of a graphics processing channel by issuing an index related to the graphics processing channel. The graphics processing apparatus also includes a processing core connected to the scheduler. The processing core is configured to service the graphics processing channel by: (i) correlating the index with a memory location at which an instance block for the graphics processing channel is stored; and (ii) accessing the instance block stored at the memory location.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: October 4, 2011
    Assignee: Nvidia Corporation
    Inventors: Jeffrey M. Smith, Shail Dave, Wei-Je Huang, Lincoln G. Garlick, Paolo E. Sabella
  • Patent number: 7535433
    Abstract: A system and method for modifying the configuration of one or more graphics adapters and one or more displays without rebooting the system allows a user to quickly transition between different graphics adapter/display configurations. A single display driver interfaces between the operating system and the one or more graphics devices. The display driver reconfigures the one or more graphics devices to change the adapter/display configuration without shutting down or rebooting the system. Unlike a conventional system reboot performed by the operating system, the display driver checks that there are no memory leaks or error conditions during the reconfiguration.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: May 19, 2009
    Assignee: NVIDIA Corporation
    Inventors: Herbert O. Ledebohm, Todd Michael Poynter, Shail Dave, Mark A. Einkauf, Kevin J. Kranzusch
  • Patent number: 7467289
    Abstract: Software can freeze portions of a pipeline operation in a processor by asserting a predetermined freeze register in the processor. The processor halts operations relating to portions of a common pipeline processing in response to an asserted freeze register. Processor resources that operate downstream from the common pipeline continue to process any scheduled instructions. The processor is prevented from initiating any context switching in which a processor resource is allocated to a different channel. The processor stops supplying any additional data to downstream resources and ensures that the interface to downstream resources is clear of previously sent data. The processor prevents state machines from making additional requests. The processor asserts an acknowledgement indication in response to the freeze assertion when the processing has reached a stable state. Software is allowed to manipulate states and registers within the processor. Clearing the freeze register allows processing to resume.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: December 16, 2008
    Assignee: NVIDIA Corporation
    Inventors: Lincoln G. Garlick, Vikramjeet Singh, David W. Nuechterlein, Shail Dave, Jeffrey M. Smith, Paolo E. Sabella, Dennis K. Ma
  • Publication number: 20070268296
    Abstract: A system and method for modifying the configuration of one or more graphics adapters and one or more displays without rebooting the system allows a user to quickly transition between different graphics adapter/display configurations. A single display driver interfaces between the operating system and the one or more graphics devices. The display driver reconfigures the one or more graphics devices to change the adapter/display configuration without shutting down or rebooting the system. Unlike a conventional system reboot performed by the operating system, the display driver checks that there are no memory leaks or error conditions during the reconfiguration.
    Type: Application
    Filed: May 18, 2006
    Publication date: November 22, 2007
    Inventors: Herbert O. Ledebohm, Todd Michael Poynter, Shail Dave, Mark A. Einkauf, Kevin J. Kranzusch