Abstract: A technique for reducing jitter in an oscillating signal generated by an oscillator circuit includes reducing feedback of gate leakage current while increasing electrostatic discharge protection and reducing regulated power supply requirements of the oscillator circuit, as compared to conventional oscillator circuits. A circuit includes a first integrated circuit terminal and a thick gate native transistor of a first conductivity type having a first gate terminal having a first gate thickness. The first gate terminal is coupled to the first integrated circuit terminal. The thick gate native transistor has a first threshold voltage. The thick gate native transistor is configured as a source follower. The circuit includes a second transistor of the first conductivity type having a second gate terminal with a second gate thickness less than the first gate thickness. The second gate terminal is coupled to a source terminal of the thick gate native transistor.

Abstract: A technique for reducing jitter in an oscillating signal generated by an oscillator circuit includes reducing feedback of gate leakage current while increasing electrostatic discharge protection and reducing regulated power supply requirements of the oscillator circuit, as compared to conventional oscillator circuits. A circuit includes a first integrated circuit terminal and a thick gate native transistor of a first conductivity type having a first gate terminal having a first gate thickness. The first gate terminal is coupled to the first integrated circuit terminal. The thick gate native transistor has a first threshold voltage. The thick gate native transistor is configured as a source follower. The circuit includes a second transistor of the first conductivity type having a second gate terminal with a second gate thickness less than the first gate thickness. The second gate terminal is coupled to a source terminal of the thick gate native transistor.

Abstract: A number of designs for differential floating gate nonvolatile memories and memory arrays utilize differential pFET floating gate transistors to store information. Methods of implementing such memories and memory arrays together with methods of operation and test associated with such memories and memory arrays are presented.

Abstract: Methods and apparatuses prevent overtunneling in pFET-based nonvolatile floating gate memory (NVM) cells. During a tunneling process, in which charge carriers are removed from a floating gate of a pFET-based NVM cell, a channel current of a memory cell transistor is monitored and compared to a predetermined minimum channel current required to maintain a conducting channel in an injection transistor of the memory cell. When the monitored channel current drops below the predetermined minimum channel current, charge carriers are injected onto the floating gate by impact-ionized hot-electron injection (IHEI) so that overtunneling is avoided.

Abstract: Methods and apparatuses prevent overtunneling in pFET-based nonvolatile floating gate memory (NVM) cells. During a tunneling process, in which charge carriers are removed from a floating gate of a pFET-based NVM cell, a channel current of a memory cell transistor is monitored and compared to a predetermined minimum channel current required to maintain a conducting channel in an injection transistor of the memory cell. When the monitored channel current drops below the predetermined minimum channel current, charge carriers are injected onto the floating gate by impact-ionized hot-electron injection (IHEI) so that overtunneling is avoided.

Abstract: A number of designs for differential floating gate nonvolatile memories and memory arrays utilize differential pFET floating gate transistors to store information. Methods of implementing such memories and memory arrays together with methods of operation and test associated with such memories and memory arrays are presented.

Abstract: An electrically erasable programmable read only memory (EEPROM) cell that uses differential pFET floating-gate transistors as its core.