Patents by Inventor Shailaja Chenumalla

Shailaja Chenumalla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High speed, scalable microcode based instruction decoder for processors using split microROM access, dynamic generic microinstructions, and microcode with predecoded instruction information
    Patent number: 6105125
    Abstract: A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from the instruction prefetch buffers. Information bits about the instruction are added to the tables at no extra cost and enable the faster decode of the instruction. The present invention includes the decode of an instruction using an entry ROM, which contains information regarding the instruction that can directly be used in generating the decoder outputs. This information is also used in selecting the correct ROM entry, thus enhancing the flexibility of the decoder, and to dynamically generate a generic microcode entry. Thus, microcode space requirements are reduced. A generic microcode instruction is used for commonly used, similar macroinstructions. This avoids duplication of microcode instructions and thus reduces the required microcode space.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: August 15, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Mario Nemirovsky, Shailaja Chenumalla