Abstract: Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing instructions before a checkpoint is generated. When executing instructions before the checkpoint is generated, the processor is configured to perform limited or no merging of stores into existing entries in the store queue. Then, upon detecting a predetermined condition, the processor is configured to generate a checkpoint. After generating the checkpoint, the processor is configured to continue to execute instructions. When executing instructions after the checkpoint is generated, the processor is configured to freely merge subsequent stores into post-checkpoint entries in the store queue.

Abstract: One embodiment of the present invention provides a system that synchronizes threads on a multi-threaded processor. The system starts by executing instructions from a multi-threaded program using a first thread and a second thread. When the first thread reaches a predetermined location in the multi-threaded program, the first thread executes a Start-Transactional-Execution (STE) instruction to commence transactional execution, wherein the STE instruction specifies a location to branch to if transactional execution fails. During the subsequent transactional execution, the first thread accesses a mailbox location in memory (which is also accessible by the second thread) and then executes instructions that cause the first thread to wait.

Abstract: Embodiments of the present invention provide a system that handles load-marked and store-marked cache lines. Upon asserting a load-mark or a store-mark for a cache line during a given phase of operation, the system adds an entry to a private buffer and in doing so uses an address of the cache line as a key for the entry in the private buffer. The system also updates the entry in the private buffer with information about the load-mark or store-mark and uses pointers for the entry and for the last entry added to the private buffer to add the entry to a sequence of private buffer entries placed during the phase of operation. The system then uses the entries in the private buffer to remove the load-marks and store-marks from cache lines when the phase of operation is completed.

Abstract: One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a load instruction during transactional execution of a block of instructions, the system determines whether the load instruction is a monitored load instruction or an unmonitored load instruction. If the load instruction is a monitored load instruction, the system performs the load operation, and load-marks a cache line associated with the load instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the load instruction is an unmonitored load instruction, the system performs the load operation without load-marking the cache line.

Abstract: Some embodiments of the present invention provide a system for operating a store queue, wherein the store queue buffers stores that are waiting to be committed to a memory system in a processor. During operation, the system examines an entry at the head of the store queue. If the entry contains a membar token, the system examines an unacknowledged counter that keeps track of the number of store operations that have been sent from the store queue to the memory system but have not been acknowledged as being committed to the memory system. If the unacknowledged counter is non-zero, the system waits until the unacknowledged counter equals zero, and then removes the membar token from the store queue.

Abstract: Embodiments of the present invention provide a system that dynamically reconfigures memory. During operation, the system determines that a virtual memory page is to be reconfigured from an original virtual-address-to-physical-address mapping to a new virtual-address-to-physical-address mapping. The system then determines a new real address mapping for a set of virtual addresses in the virtual memory page by selecting a range of real addresses for the virtual addresses that are arranged according to the new virtual-address-to-physical-address mapping. Next, the system temporarily disables accesses to the virtual memory page. Then, the system copies data from real address locations indicated by the original virtual-address-to-physical-address mapping to real address locations indicated by the new virtual-address-to-physical-address mapping. Next, the system updates the real-address-to-physical-address mapping for the page, and re-enables accesses to the virtual memory page.

Abstract: Embodiments of the present invention provide a system that buffers stores on a processor that supports speculative execution. The system starts by buffering a store into an entry in the store queue during a speculative execution mode. If an entry for the store does not already exist in the store queue, the system writes the store into an available entry in the store queue and updates a byte mask for the entry. Otherwise, if an entry for the store already exists in the store queue, the system merges the store into the existing entry in the store queue and updates the byte mask for the entry to include information about the newly merged store. The system then forwards the data from the store queue to subsequent dependent loads.

Abstract: A system that facilitates improving performance of a processor during scout mode. During a normal-execution mode, the system executes instructions for using main thread. Upon encountering a stall condition during execution of the main thread, the system generates a checkpoint. The system then enters a scout mode, wherein instructions are speculatively executed by a speculative thread to prefetch future memory references, but results are not committed to the architectural state of the processor. Upon encountering a memory reference during scout mode, the system issues a prefetch for the memory reference. If the stall condition that caused the processor to enter scout mode is resolved, the system uses the checkpoint to resume execution of the main thread from the instruction that caused the stall condition, and simultaneously continues executing instructions in scout mode using the speculative thread from the point where the speculative thread left off.

Abstract: A technique recovers return address stack (RAS) content and restores alignment of a RAS top-of-stack (TOS) pointer for occurrences of mispredictions due to speculative operation, out-of-order instruction processing, and exception handling. In at least one embodiment of the invention, an apparatus includes a speculative execution processor pipeline, a first structure for maintaining return addresses relative to instruction flow at a first stage of the pipeline, at least a second structure for maintaining return addresses relative to instruction flow at a second stage of the pipeline. The second stage of the pipeline is deeper in the pipeline than the first stage. The apparatus includes circuitry operable to reproduce at least return addresses from the second structure to the first structure.

Abstract: A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.

Abstract: One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a store instruction during transactional execution of a block of instructions, the system determines whether the store instruction is a monitored store instruction or an unmonitored store instruction. If the store instruction is a monitored store instruction, the system performs the store operation, and store-marks a cache line associated with the store instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the store instruction is an unmonitored store instruction, the system performs the store operation without store-marking the cache line.

Abstract: One embodiment of the present invention provides a system that facilitates load reordering through cacheline marking. During operation, the system receives a load operation to be executed. Next, the system determines whether a cacheline for the load has been load-marked by a thread which is performing the load. If so, the system performs the load. Otherwise, the system obtains the cacheline and subsequently attempts to load-mark the cacheline. If the cacheline is successfully load-marked, the system performs the load.

Abstract: One embodiment of the present invention provides a system that prevents store starvation in a computer system that supports marked coherence. The system starts by receiving a store instruction to be executed. The system then determines whether a cache line to which the store is directed is load-marked. If so, the system delays the store operation and asserts a store-requested flag in the metadata for the cache line, wherein when the store-requested flag is asserted, no subsequent load-marks can be placed on the cache line. Then, when all of the load-marks have been removed from the cache line, the system completes the store operation.

Abstract: A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.

Abstract: A computer processor pipeline has both an architectural register file and a working register file. The lifetime of an entry in the working register file is determined by a predetermined number of instructions passing through a specified stage in the pipeline after the location in the working register file is allocated for an instruction. The size of the working register file is selected based upon performance characteristics. A working register file creditor indicator is coupled to the front end pipeline portion and to the back end pipeline portion. The working register file credit indicator is monitored to prevent a working register file overflow. When the a location in the architectural register file is read early, the location is monitored to determine whether the location is written to prior to issuance of the instruction associated with the early read.

Abstract: One embodiment of the present invention provides a system for measuring processor performance during speculative-execution. The system starts by executing instructions in a normal-execution mode. The system then enters a speculative-execution episode wherein instructions are speculatively executed without being committed to the architectural state of the processor. While entering the speculative-execution episode the system enables a speculative execution monitor. The system then uses the speculative execution monitor to monitor instructions during the speculative-execution episode to record data values relating to the speculative-execution episode. Upon returning to normal-execution mode, the system disables the speculative execution monitor. The data values recorded by the speculative execution monitor facilitate measuring processor performance during speculative execution.

Abstract: One embodiment of the present invention provides a system that facilitates store reordering through cacheline marking. During operation, the system receives a memory operation which is directed to a cacheline. Next, the system determines whether a thread which is performing the memory operation has set a store-mark for the cacheline. If the thread has set the store-mark for the cacheline, the system performs the memory operation. Otherwise, the system determines if the cacheline has been store-marked by another thread. If so, the system delays the memory operation. On the other hand, if the cacheline has not been store-marked by another thread, the system performs the memory operation.

Abstract: One embodiment of the present invention provides a system that executes a transaction on a multi-threaded processor. The system starts by executing the transaction in a “transaction-pending mode,” which involves placing load-marks or store-marks on cache lines loaded from or stored to during transaction-pending mode and also buffers store operations in a store queue. Upon encountering a store queue overflow, the system continues to execute the transaction in a “store-queue-overflow mode,” which involves placing load-marks or store-marks on cache lines loaded from or stored to during store-queue-overflow mode and discards store data which does not fit into the store queue during store operations. Upon completing the transaction in the store-queue-overflow mode, the system re-executes the transaction in a “repeating-transaction mode,” which involves executing the instructions in the transaction non-speculatively, which allows the store operations to commit to the memory hierarchy.

Abstract: One embodiment of the present invention provides a system that facilitates efficient transactional execution. During operation, the system executes a starvation-avoiding transaction for a thread, wherein executing the starvation-avoiding transaction involves: (1) placing load-marks on cache lines which are loaded during the starvation-avoiding transaction; (2) placing store-marks on cache lines which are stored to during the starvation-avoiding transaction; and (3) writing a timestamp value into metadata for load-marked and store-marked cache lines. While the thread is executing the starvation-avoiding transaction, the system prevents other threads from executing another starvation-avoiding transaction. Whereby the load-marks and store-marks prevent interfering accesses from other threads to the cache lines during the starvation-avoiding transaction.

Abstract: Some embodiments of the present invention provide a system that avoids deadlock while attempting to acquire store-marks on cache lines. During operation, the system keeps track of store-mark requests that arise during execution of a thread, wherein a store-mark on a cache line indicates that one or more associated store buffer entries are waiting to be committed to the cache line. In this system, store-mark requests are processed in a pipelined manner, which allows a store-mark request to be initiated before preceding store-mark requests for the same thread complete. Next, if a store-mark request fails, within a bounded amount of time, the system removes or prevents store-marks associated with younger store-mark requests for the same thread, thereby avoiding a potential deadlock that can arise when one or more other threads attempt to store-mark the same cache lines.