Patents by Inventor Shailendra Desai

Shailendra Desai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11914440
    Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: February 27, 2024
    Assignee: Google LLC
    Inventors: Shailendra Desai, Mark Pearce, Amit Jain, Jaymin Patel
  • Patent number: 11640362
    Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: May 2, 2023
    Assignee: Google LLC
    Inventors: Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain, Mark Pearce
  • Publication number: 20220291730
    Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 15, 2022
    Applicant: Google LLC
    Inventors: Shailendra Desai, Mark Pearce, Amit Jain, Jaymin Patel
  • Publication number: 20220214731
    Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Applicant: Google LLC
    Inventors: Shailendra Desai, Mark Pearce, Amit Jain, Jaymin Patel
  • Patent number: 11340671
    Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 24, 2022
    Assignee: Google LLC
    Inventors: Shailendra Desai, Mark Pearce, Amit Jain, Jaymin Patel
  • Publication number: 20210294762
    Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.
    Type: Application
    Filed: April 12, 2021
    Publication date: September 23, 2021
    Applicant: Google LLC
    Inventors: Shailendra DESAI, Robert TOTTE, Juan SIERRA, Parimal GAIKWAD, Amit JAIN, Mark PEARCE
  • Patent number: 11003604
    Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: May 11, 2021
    Assignee: PROVINO TECHNOLOGIES, INC.
    Inventors: Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain, Mark Pearce
  • Patent number: 10853282
    Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: December 1, 2020
    Assignee: PROVINO TECHNOLOGIES, INC.
    Inventors: Shailendra Desai, Mark Pearce, Amit Jain, Rutul Bhatt
  • Patent number: 10838891
    Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: November 17, 2020
    Assignee: PROVINO TECHNOLOGIES, INC.
    Inventors: Shailendra Desai, Mark Pearce, Amit Jain, Rutul Bhatt
  • Patent number: 10585825
    Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 10, 2020
    Assignee: PROVINO TECHNOLOGIES, INC.
    Inventors: Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain, Mark Pearce
  • Publication number: 20190303325
    Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventors: Shailendra DESAI, Mark PEARCE, Amit JAIN, Rutul BHATT
  • Publication number: 20190303320
    Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 3, 2019
    Inventors: Shailendra DESAI, Robert TOTTE, Juan SIERRA, Parimal GAIKWAD, Amit JAIN, Mark PEARCE
  • Publication number: 20190302861
    Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventors: Shailendra DESAI, Mark PEARCE, Amit JAIN, Jaymin PATEL
  • Publication number: 20190303326
    Abstract: Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventors: Shailendra DESAI, Mark PEARCE, Amit JAIN, Rutul BHATT
  • Publication number: 20190303777
    Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventors: Shailendra DESAI, Mark PEARCE, Amit JAIN, Jaymin PATEL
  • Publication number: 20190303778
    Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventors: Shailendra DESAI, Mark PEARCE, Amit JAIN, Jaymin PATEL
  • Publication number: 20190303217
    Abstract: Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 3, 2019
    Inventors: Shailendra Desai, Robert Totte, Juan Sierra, Parimal Gaikwad, Amit Jain, Mark Pearce
  • Publication number: 20070047443
    Abstract: In one embodiment, a controller is configured to receive a flow control packet from a link partner on a communication medium. The flow control packet includes a channel indication that indicates one or more channels. The controller is configured to inhibit transmission of packets from at least one channel specified by the channel indication and to permit transmission of packets from channels not specified in the channel indication. The controller may also be configured to transmit the flow control packet in response to detecting a need to flow control one or more channels from the link partner.
    Type: Application
    Filed: August 25, 2005
    Publication date: March 1, 2007
    Applicant: P.A. Semi, Inc.
    Inventors: Shailendra Desai, Mark Hayter
  • Publication number: 20070047572
    Abstract: In one embodiment, a system comprises a communication medium; a first controller coupled to the communication medium; and a second controller coupled to the communication medium. The first controller is configured to interrupt transmission of a packet on the communication medium to the second controller subsequent to transmission of a first portion of the packet. The first controller is configured to transmit at least one control symbol on the communication medium in response to interrupting transmission of the packet, and wherein the first controller is configured to continue transmission of the packet with a second portion of the packet. The controller(s) may include, in some embodiments, a media access controller and a physical coding sublayer.
    Type: Application
    Filed: August 25, 2005
    Publication date: March 1, 2007
    Applicant: P.A. Semi, Inc.
    Inventors: Shailendra Desai, Mark Hayter
  • Publication number: 20050172060
    Abstract: A distributed arbitration scheme includes arbiters with each agent. The arbiters receive request signals indicating which agents are arbitrating for the bus. Additionally, the agent currently using the bus broadcasts an agent identifier assigned to that agent. The arbiters receive the agent identifier and use the agent identifier as an indication of the winner of the preceding arbitration. Accordingly, the arbiters determine if the corresponding agent wins the arbitration, but may not attempt to calculate which other agent wins the arbitration. In one embodiment, the arbiter maintains a priority state indicative of which of the other agents are higher priority than the corresponding agent and which of the other agents are lower priority. In one implementation, the bus may be a split transaction bus and thus each requesting agent may include an address arbiter and each responding agent may include a data arbiter.
    Type: Application
    Filed: March 1, 2005
    Publication date: August 4, 2005
    Inventors: Joseph Rowlands, David Anderson, Shailendra Desai