Patents by Inventor Shailendra Sharad
Shailendra Sharad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240104043Abstract: Embodiments herein relate to a module which can be inserted into or removed from a computing device by a user. The module includes an input-output port which is configured for a desired specification, such as USB-A, USB-C, Thunderbolt, DisplayPort or HDMI. The port can be provided on an expansion card such as an M.2 card for communicating with a host platform. The host platform can communicate with different types of modules in a standardized way so that complexity and costs are reduced. In another aspect, with a dual port module, the host platform can concurrently send/receive power through one port and send/receive data from the other port.Type: ApplicationFiled: September 22, 2022Publication date: March 28, 2024Inventors: Shailendra Singh Chauhan, Nirmala Bailur, Reza M. Zamani, Jackson Chung Peng Kong, Charuhasini Sunder Raman, Venkataramani Gopalakrishnan, Chuen Ming Tan, Sreejith Satheesakurup, Karthi Kaliswamy, Venkata Mahesh Gunnam, Yi Jen Huang, Kie Woon Lim, Dhinesh Sasidaran, Pik Shen Chee, Venkataramana Kotakonda, Kunal A. Shah, Ramesh Vankunavath, Siva Prasad Jangili Ganga, Ravali Pampala, Uma Medepalli, Tomer Savariego, Naznin Banu Wahab, Sindhusha Kodali, Manjunatha Venkatarauyappa, Surendar Jeevarathinam, Madhura Shetty, Deepak Sharma, Rohit Sharad Mahajan
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Patent number: 9842642Abstract: An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC1, . . . , BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a static random access memory architecture. The first and the second bit cells (BC1, BC2) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C1, C2) of the memory cell array (100). During a write access to the first bit cell (BC1), the first bit cell (BC1) undergoes a write operation, whereas the second bit cell (BC2) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit uses a two-phase write scheme to improve the write-ability in low operating voltage environment.Type: GrantFiled: August 17, 2015Date of Patent: December 12, 2017Assignee: Synopsys, Inc.Inventors: M. Sultan M. Siddiqui, Shailendra Sharad, Hemant Vats, Amit Khanuja
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Publication number: 20160049191Abstract: An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC1, . . . , BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a static random access memory architecture. The first and the second bit cells (BC1, BC2) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C1, C2) of the memory cell array (100). During a write access to the first bit cell (BC1), the first bit cell (BC1) undergoes a write operation, whereas the second bit cell (BC2) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit uses a two-phase write scheme to improve the write-ability in low operating voltage environment.Type: ApplicationFiled: August 17, 2015Publication date: February 18, 2016Inventors: Sultan M. Siddiqui, Shailendra Sharad, Hemant Vats, Amit Khanuja
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Patent number: 8830771Abstract: A memory device includes a memory array comprising a including of memory cells, and control circuitry coupled to the memory array. The control circuitry includes write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel combination of additional memory cells may comprise a mini-array that includes centrally-located active memory cells surrounded by dummy memory cells. In an arrangement in which the write signal generation circuitry includes a clock latch, the parallel combination of additional memory cells may be coupled between a clock output of the clock latch and a reset input of the clock latch.Type: GrantFiled: May 17, 2012Date of Patent: September 9, 2014Assignee: LSI CorporationInventors: Shailendra Sharad, Manish Umedlal Patel, Diwakar Ramadasu, Setti Shanmukheswara Rao
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Patent number: 8605530Abstract: A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor.Type: GrantFiled: November 26, 2012Date of Patent: December 10, 2013Assignee: STMicroelectronics International N.V.Inventors: Sanjay Kumar Yadav, G Penaka Phani, Shailendra Sharad
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Publication number: 20130308398Abstract: A memory device includes a memory array comprising a plurality of memory cells, and control circuitry coupled to the memory array. The control circuitry comprises write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel combination of additional memory cells may comprise a mini-array that includes centrally-located active memory cells surrounded by dummy memory cells. In an arrangement in which the write signal generation circuitry comprises a clock latch, the parallel combination of additional memory cells may be coupled between a clock output of the clock latch and a reset input of the clock latch.Type: ApplicationFiled: May 17, 2012Publication date: November 21, 2013Applicant: LSI CorporationInventors: Shailendra Sharad, Manish Umedlal Patel, Diwakar Ramadasu, Setti Shanmukheswara Rao
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Publication number: 20130258794Abstract: A memory device includes a memory array comprising a plurality of memory cells arranged in rows and columns, and sensing circuitry coupled to the memory array. The sensing circuitry comprises a plurality of output sense amplifiers configured to sense stored data associated with respective columns of the memory array, and sense amplifier control circuitry configured to generate a sense amplifier control signal for application to control inputs of respective ones of the output sense amplifiers. The sense amplifier control circuitry comprises reaction time tracking circuitry including at least one dummy sense amplifier configured to track reaction time of one or more of the output sense amplifiers, with the sense amplifier control signal being generated at least in part responsive to an output signal of the dummy sense amplifier.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Applicant: LSI CorporationInventors: Shailendra Sharad, Manish Umedlal Patel, Setti Shanmukheswara Rao
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Patent number: 8477550Abstract: A sensing circuit for use in a semiconductor memory device includes first and second conducting lines for conducting a bit signal to and from a memory cell. The circuit further includes a sense amplifier coupled to the first and second conducting lines for sensing a bit signal, a charge storing element for generating a predefined potential, and first and second switching element respectively coupled to the first and second conducting lines. The first and second switching elements are selectively controllable to connect the first and second conducting line to the charge storing element so as to induce the generated predefined voltage on the first or second conducting lines.Type: GrantFiled: August 16, 2010Date of Patent: July 2, 2013Assignee: STMicroelectronics International N.V.Inventors: Shailendra Sharad, Rupak Kundu, G. Penaka Phani
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Publication number: 20110273923Abstract: A sensing circuit for use in a semiconductor memory device includes first and second conducting lines for conducting a bit signal to and from a memory cell. The circuit further includes a sense amplifier coupled to the first and second conducting lines for sensing a bit signal, a charge storing element for generating a predefined potential, and first and second switching element respectively coupled to the first and second conducting lines. The first and second switching elements are selectively controllable to connect the first and second conducting line to the charge storing element so as to induce the generated predefined voltage on the first or second conducting lines.Type: ApplicationFiled: August 16, 2010Publication date: November 10, 2011Applicant: STMICROELECTRONICS PVT.LTDInventors: Shailendra Sharad, Rupak Kundu, G. Penaka Phani