Patents by Inventor Shailesh Ganapat Ghotgalkar
Shailesh Ganapat Ghotgalkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990914Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.Type: GrantFiled: December 14, 2021Date of Patent: May 21, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shailesh Ganapat Ghotgalkar, Wei Fu, Venkatseema Das
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Publication number: 20230068811Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.Type: ApplicationFiled: October 18, 2022Publication date: March 2, 2023Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Prasanth Viswanathan Pillai, Rajeev Suvarna, Saya Goud Langadi, Shailesh Ganapat Ghotgalkar
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Publication number: 20230006681Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.Type: ApplicationFiled: September 12, 2022Publication date: January 5, 2023Applicant: Texas Instruments IncorporatedInventors: Shailesh Ganapat GHOTGALKAR, Wei FU, Venkatseema DAS, Jiankun HU
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Patent number: 11474151Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.Type: GrantFiled: December 30, 2020Date of Patent: October 18, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prasanth Viswanathan Pillai, Rajeev Suvarna, Saya Goud Langadi, Shailesh Ganapat Ghotgalkar
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Patent number: 11444626Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.Type: GrantFiled: August 26, 2021Date of Patent: September 13, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shailesh Ganapat Ghotgalkar, Wei Fu, Venkatseema Das, Jiankun Hu
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Patent number: 11385862Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.Type: GrantFiled: October 13, 2020Date of Patent: July 12, 2022Assignee: Texas Instmments IncorporatedInventor: Shailesh Ganapat Ghotgalkar
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Publication number: 20220206065Abstract: Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Inventors: Prasanth Viswanathan Pillai, Rajeev Suvarna, Saya Goud Langadi, Shailesh Ganapat Ghotgalkar
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Publication number: 20220209776Abstract: In described examples, a counter system includes a counter, a parity detector, a toggle flop, and a comparator. The counter iterates a count through a set of binary states in response to a clock signal, so that a binary value of a single bit of the count changes at each iteration. The parity detector detects the parity of the count. The toggle flop output is coupled to the toggle flop input. The toggle flop outputs a binary flop value. The binary flop value toggles between zero and one in response to the toggle flop input and the clock signal. The comparator compares the parity of the count and the toggle flop output, and outputs a first comparator value if the parity of the count and the toggle flop output are the same, and a second comparator value if the parity of the count and the toggle flop output are different.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Inventors: Shailesh Ganapat Ghotgalkar, Prasanth Viswanathan Pillai, Maheedhar Janaki Jalasutram
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Patent number: 11374576Abstract: In described examples, a counter system includes a counter, a parity detector, a toggle flop, and a comparator. The counter iterates a count through a set of binary states in response to a clock signal, so that a binary value of a single bit of the count changes at each iteration. The parity detector detects the parity of the count. The toggle flop output is coupled to the toggle flop input. The toggle flop outputs a binary flop value. The binary flop value toggles between zero and one in response to the toggle flop input and the clock signal. The comparator compares the parity of the count and the toggle flop output, and outputs a first comparator value if the parity of the count and the toggle flop output are the same, and a second comparator value if the parity of the count and the toggle flop output are different.Type: GrantFiled: December 30, 2020Date of Patent: June 28, 2022Assignee: Texas Instruments IncorporatedInventors: Shailesh Ganapat Ghotgalkar, Prasanth Viswanathan Pillai, Maheedhar Janaki Jalasutram
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Publication number: 20220103181Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.Type: ApplicationFiled: December 14, 2021Publication date: March 31, 2022Inventors: Shailesh Ganapat Ghotgalkar, Wei Fu, Venkatseema Das
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Patent number: 11239847Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.Type: GrantFiled: July 28, 2020Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shailesh Ganapat Ghotgalkar, Wei Fu, Venkatseema Das
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Publication number: 20210384913Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.Type: ApplicationFiled: August 26, 2021Publication date: December 9, 2021Inventors: Shailesh Ganapat GHOTGALKAR, Wei FU, Venkatseema DAS, Jiankun HU
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Patent number: 11133807Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.Type: GrantFiled: December 4, 2019Date of Patent: September 28, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shailesh Ganapat Ghotgalkar, Wei Fu, Venkatseema Das, Jiankun Hu
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Publication number: 20210026597Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.Type: ApplicationFiled: October 13, 2020Publication date: January 28, 2021Inventor: Shailesh Ganapat Ghotgalkar
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Publication number: 20200403622Abstract: A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.Type: ApplicationFiled: December 4, 2019Publication date: December 24, 2020Inventors: Shailesh Ganapat GHOTGALKAR, Wei FU, Venkatseema DAS, Jiankun HU
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Publication number: 20200358446Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.Type: ApplicationFiled: July 28, 2020Publication date: November 12, 2020Inventors: Shailesh Ganapat Ghotgalkar, Wei Fu, Venkatseema Das
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Patent number: 10817257Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.Type: GrantFiled: April 22, 2019Date of Patent: October 27, 2020Assignee: Texas Instruments IncorporatedInventor: Shailesh Ganapat Ghotgalkar
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Patent number: 10727841Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.Type: GrantFiled: October 22, 2018Date of Patent: July 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shailesh Ganapat Ghotgalkar, Wei Fu, Venkatseema Das
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Publication number: 20200127667Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.Type: ApplicationFiled: October 22, 2018Publication date: April 23, 2020Inventors: Shailesh Ganapat Ghotgalkar, Wei Fu, Venkatseema Das
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Publication number: 20190310825Abstract: A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.Type: ApplicationFiled: April 22, 2019Publication date: October 10, 2019Inventor: Shailesh Ganapat Ghotgalkar