Patents by Inventor Shailesh I. Shah

Shailesh I. Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130346926
    Abstract: Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed.
    Type: Application
    Filed: November 9, 2012
    Publication date: December 26, 2013
    Applicant: ALGOTOCHIP CORPORATION
    Inventors: Anand Pandurangan, Satish Padmanabhan, Siva Selvaraj, Shailesh I. Shah, Krishna Kumar Gadiyaram, Gagan Bihari Rath, Fuk Ho Pius Ng, Ananth Durbha, Suresh Kadiyala
  • Patent number: 6523055
    Abstract: A multiplication accumulation circuit (abbreviated as “MAC”) has five input buses that carry signals for operands A, B, C, D and E, a control bus that carries signals for controlling the operations performed on the received operands, and an output bus that carries a signal generated by the MAC. Each of operands A, B, C and D can be four different operands that are used as follows by the MAC: (1) to perform two multiplications simultaneously, and (2) to perform an addition of the products of the two multiplications and the fifth operand E, e.g. generate on the output bus a signal of value A*C+B*D+E. Alternatively, operands A and B can be, respectively, the upper and lower halves of a first double word to be used as a multiplicand. Similarly, operands C and D can be the upper and lower halves of a second double word to be used as a multiplier.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: February 18, 2003
    Assignee: LSI Logic Corporation
    Inventors: Robert K. Yu, Satish Padmanabhan, Chakra R. Srivatsa, Shailesh I. Shah
  • Patent number: 5987603
    Abstract: An instruction (also called a "bit reversal instruction") for reversing the order of bits in an input signal is implemented by reusing one or more components in a datapath normally found in a processor. Specifically, a bit reversal instruction is implemented by reuse of a shifter unit normally used in a datapath to shift bits of an input signal. The shifter unit includes three stages: a first stage formed by a number of input multiplexers, a second stage formed by, for example, a left shifter, and a third stage formed by a number of output multiplexers. When using a left shifter to implement the bit reversal instruction, the input multiplexers are not used. Instead, the left shifter is used to shift bits of the input signal left by a number that is inverse of the number of bits to be reversed. Thereafter, the output multiplexers reverse the order of bits generated by the left shifter, thereby completing the bit reversal instruction.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: November 16, 1999
    Assignee: LSI Logic Corporation
    Inventor: Shailesh I. Shah