Abstract: A biasing circuit for reading a selected cell of an array of semiconductor memory cells in which each cell is coupled to a drain-column line, a source-column line and a wordline, with the selected cell coupled to a selected drain-column line, a selected source-column line, and a selected wordline.

Abstract: A two-transistor programmable memory cell (FIG. 1A, 20) with one vertical floating gate transistor (VT) and one planar transistor (PT)--the planar transistor can be optimized for programming with low current (longer channel length and narrower channel width), while the vertical transistor can be optimized for reading with high current (shorter channel length and wider channel width). The vertical transistor is formed in a trench (22) with a source region (15) and a sub-source VT drain region (23). The planar transistor includes the source region (15) and a co-planar PT drain region (27).

Abstract: A high speed circuit for detecting input or address transitions at a terminal of an integrated circuit logic array. The circuit utilizes N-channel leaker transistors to control the widths of and P-channel transistors to control the risetimes of output pulses and utilizes inverters and OR circuits to sense input or address transitions of both polarities.

Abstract: A circuit for providing a "power-up" signal pulse in response to energization of an integrated circuit logic array by a power supply. The circuit is comprised of a pulse-generating circuit and of an optional pulse-delay means. The pulse-generating circuit means detects the presence or absence of change in energization voltage potential and, in response to energization, develops an output pulse using ratioed complementary-metal-oxide-semiconductor (CMOS) logic to detect energization status during the ramp increase of the supply voltage. A feedback circuit is used to detect completion of the ramp increase and to deactivate the circuit to minimize power required for steady-state operation. The optional pulse-delay means is illustrated as narrow-width, long-channel CMOS inverters with optional capacitor loading.

Abstract: A single-ended sense amplifier for use in integrated-circuit logic arrays. The sense amplifier circuit uses five field-effect transistors in a unique configuration that uses positive feedback to increase the output speed of response while at the same time allowing layout in the narrow pitch of one bitline of an integrated-circuit logic array.