Abstract: There is provided a method of fabrication an integrated circuit comprising providing a substrate with a bond pad formed thereover, the bond pad having a top surface for the formation of bonding connections. A passivation layer is provided over the bond pad followed by an overlying masking layer. The passivation layer is subsequently etched in accordance with the masking layer to form a patterned passivation layer with an opening that exposes a portion of the top surface of the bond pad. After etching the passivation layer, the mask layer is removed by a plasma resist strip followed by a wet solvent clean that removes etch residue from the passivation layer etch. Finally, a bond pad protective layer is grown over the surface of the bond pad. The bond pad may be composed of aluminum and the bond pad protective layer may be aluminum oxide.

Abstract: There is provided a method of fabrication an integrated circuit comprising providing a substrate with a bond pad formed thereover, the bond pad having a top surface for the formation of bonding connections. A passivation layer is provided over the bond pad followed by an overlying masking layer. The passivation layer is subsequently etched in accordance with the masking layer to form a patterned passivation layer with an opening that exposes a portion of the top surface of the bond pad. After etching the passivation layer, the mask layer is removed by a plasma resist strip followed by a wet solvent clean that removes etch residue from the passivation layer etch. Finally, a bond pad protective layer is grown over the surface of the bond pad. The bond pad may be composed of aluminum and the bond pad protective layer may be aluminum oxide.

Abstract: A single integrated fault detection apparatus and method for detecting heat-related and non-heat-related integrated circuit defects is disclosed. In one embodiment, the present invention is an apparatus comprising a first portion for detecting non-heat-related integrated circuit defects. In this embodiment, the present invention further comprises a second portion for detecting heat-related integrated circuit defects. In the present embodiment, the second portion is integrated with the first portion to provide a single integrated fault detection apparatus such that the heat-related and the non-heat-related integrated circuit defects are detectable using only a single integrated fault detection apparatus.

Abstract: A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.

Abstract: A new test structure to locate bridging defects in a conductive layer of an integrated circuit device is achieved. The test structure comprises a line comprising a conductive layer overlying a substrate. The line is coupled to ground. A plurality of rectangles comprises the conductive layer. The rectangles are not connected to the line or to other rectangles. Near edges of the rectangles and of the line are parallel. The rectangles are floating. The test structure is used with a passive voltage contrast test in a scanning electron microscope. A test structure and method to measure critical dimensions is disclosed.

Abstract: A method for removing a silicide poly on an integrated circuit (IC) chip. Specifically, one embodiment of the present invention discloses a method for exposing a gate oxide layer with a fluorine based reactive ion etching (F-based RIE) process and immersion in a sodium hydroxide based solution. The F-based RIE damages a silicide layer that covers a polysilicon gate layer. Damage to the silicide layer allows for penetration of chemicals to a polysilicon gate layer. Immersion of the IC chip in the sodium hydroxide based solution etches away the polysilicon gate layer and lifts off the silicide layer without altering an underlying gate oxide layer. Also, another embodiment uses a solution including sodium hydroxide and sodium chloride. As such, failure analysis of the gate oxide layer can proceed without concern for damage due to the removal process.

Abstract: A method for preparing a transmission electron microscopy (TEM) sample for contact and via characterization. Specifically, one embodiment of the present invention discloses a method where an integrated circuit semiconductor chip (IC chip) is bonded to a piece of glass and attached to a sample holder. Areas of the IC chip are removed by polishing until a region surrounding a particular contact or via is exposed. The piece of glass supports the IC chip during the polishing process. The IC chip is cut using a focused ion beam to create a thin membrane suitable for TEM failure analysis. The thin membrane includes a plan-view cross-section from the particular contact or via. The cross-sectional plan-view is perpendicular to the longitudinal axis of the contact or via.

Abstract: A method for preparing a transmission electron microscopy (TEM) sample for contact and via characterization. Specifically, one embodiment of the present invention discloses a method where an integrated circuit semiconductor chip (IC chip) is bonded to a piece of glass and attached to a sample holder. Areas of the IC chip are removed by polishing until a region surrounding a particular contact or via is exposed. The piece of glass supports the IC chip during the polishing process. The IC chip is cut using a focused ion beam to create a thin membrane suitable for TEM failure analysis. The thin membrane includes a plan-view cross-section from the particular contact or via. The cross-sectional plan-view is perpendicular to the longitudinal axis of the contact or via.

Abstract: A method for removing a silicide poly on an integrated circuit (IC) chip. Specifically, one embodiment of the present invention discloses a method for exposing a gate oxide layer with a fluorine based reactive ion etching (F-based RIE) process and immersion in a sodium hydroxide based solution. The F-based RIE damages a silicide layer that covers a polysilicon gate layer. Damage to the silicide layer allows for penetration of chemicals to a polysilicon gate layer. Immersion of the IC chip in the sodium hydroxide based solution etches away the polysilicon gate layer and lifts off the silicide layer without altering an underlying gate oxide layer. Also, another embodiment uses a solution including sodium hydroxide and sodium chloride. As such, failure analysis of the gate oxide layer can proceed without concern for damage due to the removal process.