Patents by Inventor Shailesh Shah
Shailesh Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250132212Abstract: Disclosed is a QFN packaged semiconductor device, having a first major surface, an opposing second major surface and sidewalls therebetween, and comprising: a lead-frame, having a lead-frame lower surface and comprising a central die-pad region and a plurality of peripheral landing regions; a semiconductor die, attached to the die-pad on a top surface thereof; a plurality of bond-wires providing electrical connection between the semiconductor die and the plurality of peripheral landing regions; and encapsulant material, encapsulating the semiconductor die and bond-wires; wherein the encapsulant material forms a frame extending below the lead-frame lower surface, and defining the second major surface, the frame having an opening therein in a central region thereof under the semiconductor die, and wherein the sidewalls are spaced apart from the frame thereby exposing the lead-frame lower surface at the plurality of peripheral landing regions.Type: ApplicationFiled: October 18, 2024Publication date: April 24, 2025Inventors: You Ge, Zhijie Wang, Yit Meng Lee, Ankur Shailesh Shah, Amornthep Saiyajitara
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Publication number: 20250103548Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.Type: ApplicationFiled: November 14, 2024Publication date: March 27, 2025Applicant: Intel CorporationInventors: Altug Koker, Joydeep Ray, Ben Ashbaugh, Jonathan Pearce, Abhishek Appu, Vasanth Ranganathan, Lakshminarayanan Striramassarma, Elmoustapha Ould-Ahmed-Vall, Aravindh Anantaraman, Valentin Andrei, Nicolas Galoppo Von Borries, Varghese George, Yoav Harel, Arthur Hunter, JR., Brent Insko, Scott Janus, Pattabhiraman K, Mike Macpherson, Subramaniam Maiyuran, Marian Alin Petre, Murali Ramadoss, Shailesh Shah, Kamal Sinha, Prasoonkumar Surti, Vikranth Vemulapalli
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Patent number: 12210477Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.Type: GrantFiled: March 14, 2020Date of Patent: January 28, 2025Assignee: Intel CorporationInventors: Altug Koker, Joydeep Ray, Ben Ashbaugh, Jonathan Pearce, Abhishek Appu, Vasanth Ranganathan, Lakshminarayanan Striramassarma, Elmoustapha Ould-Ahmed-Vall, Aravindh Anantaraman, Valentin Andrei, Nicolas Galoppo Von Borries, Varghese George, Yoav Harel, Arthur Hunter, Jr., Brent Insko, Scott Janus, Pattabhiraman K, Mike Macpherson, Subramaniam Maiyuran, Marian Alin Petre, Murali Ramadoss, Shailesh Shah, Kamal Sinha, Prasoonkumar Surti, Vikranth Vemulapalli
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Publication number: 20240379474Abstract: A packaged semiconductor device (200) is disclosed, having a first major surface (210), a second major surface (220), and sidewalls (230) therebetween, the packaged device comprising: a moulding compound (240) around a perimeter of the device and defining at least a part of the sidewalls; a lid (250) defining the first major surface, and defining a cavity (252) within the packaged semiconductor device; wherein the lid extends from a central region, to and beyond an upper surface of the moulding compound, and comprises a lip (260) around at least part of the moulding compound; further comprising an adhesive material (270), between a top surface of the moulding compound and the lid and providing a bond therebetween. Related methods are also disclosed.Type: ApplicationFiled: May 21, 2024Publication date: November 14, 2024Inventors: Ankur Shailesh Shah, Dwight Lee Daniels, Scott M. Hayes
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Publication number: 20240361905Abstract: A software developer can use a local browser, running on a local machine of the developer in a first location to access a real device (e.g., a smart phone) at a second location, such as a datacenter. The developer can select and control the remote device, in the second location. A mirrored display of the remote device can be generated on the local machine by transmitting a video feed of the screen of the remote device to the local machine. The developer can interact with the mirrored display, and the interactions can be transmitted to the remote device. The developer can activate an accessibility mode via the local machine to test accessibility features of a program.Type: ApplicationFiled: July 9, 2024Publication date: October 31, 2024Inventors: Navinkumar Arun Singh, Ajay Pratap Singh, Tirth Shailesh Shah
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Publication number: 20240362233Abstract: Disclosed are various approaches performing distributed profiling and validation. A query is generated for profile data for data stored in a data warehouse. Then, the query for the profile data is sent to the data warehouse. The profile data is then received from the data warehouse. Later, in response to a request to load the data stored in the data warehouse into a table in a data store, a determination is made as to whether the data stored in the data warehouse complies with a validation rule.Type: ApplicationFiled: November 15, 2023Publication date: October 31, 2024Inventors: Ajeet Kumar Pandey, Ashish Sehgal, Sumit Sodhi, Pooja Baja Malhotra, Achut Perumbala, Vinay Dhingra, Purvi Shailesh Shah, Phanikalyan Cherukuri
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Patent number: 12079469Abstract: A software developer can use a local browser, running on a local machine of the developer in a first location to access a real device (e.g., a smart phone) at a second location, such as a datacenter. The developer can select and control the remote device, in the second location. A mirrored display of the remote device can be generated on the local machine by transmitting a video feed of the screen of the remote device to the local machine. The developer can interact with the mirrored display, and the interactions can be transmitted to the remote device. The developer can activate an accessibility mode via the local machine to test accessibility features of a program.Type: GrantFiled: May 12, 2023Date of Patent: September 3, 2024Assignee: BrowserStack LimitedInventors: Navinkumar Arun Singh, Ajay Pratap Singh, Tirth Shailesh Shah
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Publication number: 20240199522Abstract: Provided herein are salt and solid forms of (2E,4E)-3-methyl-5-((1S,2S)-2-methyl-2-(5,5,8,8-tetramethyl-5,6,7,8-tetrahydronaphthalen-2-yl)cyclopropyl)penta-2,4-dienoic acid, including a Tris salt form of (2E,4E)-3-methyl-5-((1S,2S)-2-methyl-2-(5,5,8,8-tetramethyl-5,6,7,8-tetrahydronaphthalen-2-yl)cyclopropyl)penta-2,4-dienoic acid, and polymorphs thereof, methods of preparing the compounds, and their uses.Type: ApplicationFiled: January 18, 2024Publication date: June 20, 2024Inventors: Vidyasagar Vuligonda, Martin E. Sanders, Shanming Kuang, Harsh Shailesh Shah
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Patent number: 12003282Abstract: Channel predictive behavior and fault analysis may be provided. A forward time value may be determined comprising a time a forward signal takes to travel from a transmitter over a channel to the receiver. Next, a reflected time value may be determined comprising a time a reflected signal takes to travel to the receiver. The reflected signal may be associated with the forward signal. A discontinuity may then be determined to exist on the channel based on the forward time value and the reflected time value. The reflected signal may be caused by the discontinuity and a high impedance or low impedance at the transmitter present after the forward signal is sent.Type: GrantFiled: February 22, 2023Date of Patent: June 4, 2024Inventors: Amendra Koul, David Nozadze, Mike Sapozhnikov, Joel Goergen, Arnav Shailesh Shah
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Publication number: 20240103718Abstract: A software developer can use a local browser, running on a local machine of the developer in a first location to access a real device (e.g., a smart phone) at a second location, such as a datacenter. The developer can select and control the remote device, in the second location. A mirrored display of the remote device can be generated on the local machine by transmitting a video feed of the screen of the remote device to the local machine. The developer can interact with the mirrored display, and the interactions can be transmitted to the remote device. The developer can activate an accessibility mode via the local machine to test accessibility features of a program.Type: ApplicationFiled: May 12, 2023Publication date: March 28, 2024Inventors: Navinkumar Arun Singh, Ajay Pratap Singh, Tirth Shailesh Shah
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Patent number: 11919848Abstract: Provided herein are salt and solid forms of (2E,4E)-3-methyl-5-((1S,2S)-2-methyl-2-(5,5,8,8-tetramethyl-5,6,7,8-tetrahydronaphthalen-2-yl)cyclopropyl)penta-2,4-dienoic acid, including a Tris salt form of (2E,4E)-3-methyl-5-((1S,2S)-2-methyl-2-(5,5,8,8-tetramethyl-5,6,7,8-tetrahydronaphthalen-2-yl)cyclopropyl)penta-2,4-dienoic acid, and polymorphs thereof, methods of preparing the compounds, and their uses.Type: GrantFiled: March 14, 2023Date of Patent: March 5, 2024Assignee: Io Therapeutics, Inc.Inventors: Vidyasagar Vuligonda, Martin E. Sanders, Shanming Kuang, Harsh Shailesh Shah
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Publication number: 20230295069Abstract: Provided herein are salt and solid forms of (2E,4E)-3-methyl-5-((1S,2S)-2-methyl-2-(5,5,8,8-tetramethyl-5,6,7,8-tetrahydronaphthalen-2-yl)cyclopropyl)penta-2,4-dienoic acid, including a Tris salt form of (2E,4E)-3-methyl-5-((1S,2S)-2-methyl-2-(5,5,8,8-tetramethyl-5,6,7,8-tetrahydronaphthalen-2-yl)cyclopropyl)penta-2,4-dienoic acid, and polymorphs thereof, methods of preparing the compounds, and their uses.Type: ApplicationFiled: March 14, 2023Publication date: September 21, 2023Inventors: Vidyasagar Vuligonda, Martin E. Sanders, Shanming Kuang, Harsh Shailesh Shah
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Publication number: 20230198639Abstract: Channel predictive behavior and fault analysis may be provided. A forward time value may be determined comprising a time a forward signal takes to travel from a transmitter over a channel to the receiver. Next, a reflected time value may be determined comprising a time a reflected signal takes to travel to the receiver. The reflected signal may be associated with the forward signal. A discontinuity may then be determined to exist on the channel based on the forward time value and the reflected time value. The reflected signal may be caused by the discontinuity and a high impedance or low impedance at the transmitter present after the forward signal is sent.Type: ApplicationFiled: February 22, 2023Publication date: June 22, 2023Applicant: Cisco Technology, Inc.Inventors: Amendra Koul, David Nozadze, Mike Sapozhnikov, Joel Goergen, Arnav Shailesh Shah
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Patent number: 11650735Abstract: A software developer can use a local browser, running on a local machine of the developer in a first location to access a real device (e.g., a smart phone) at a second location, such as a datacenter. The developer can select and control the remote device, in the second location. A mirrored display of the remote device can be generated on the local machine by transmitting a video feed of the screen of the remote device to the local machine. The developer can interact with the mirrored display, and the interactions can be transmitted to the remote device. The developer can activate an accessibility mode via the local machine to test accessibility features of a program.Type: GrantFiled: September 26, 2022Date of Patent: May 16, 2023Assignee: BrowserStack LimitedInventors: Navinkumar Arun Singh, Ajay Pratap Singh, Tirth Shailesh Shah
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Patent number: 11650904Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing real-time code analysis. One of the methods includes receiving a request to perform real-time code analysis on source code, wherein the request identifies one or more target source code elements. A plurality of real-time annotation values occurring in the source code for the target source code elements are identified. A call graph is generated for the one or more target source code elements. The call graph is traversed to identify one or more real-time violations, wherein each real-time violation is an instance in the source code that violates one or more real-time safe criteria. An output is provided that identifies one or more of the real-time violations occurring in the source code.Type: GrantFiled: December 23, 2019Date of Patent: May 16, 2023Assignee: Intrinsic Innovation LLCInventors: Abhishek Shailesh Shah, Gregory J. Prisament, Michael Beardsworth, Dmytro Hrybenko
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Patent number: 11620256Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.Type: GrantFiled: April 28, 2022Date of Patent: April 4, 2023Assignee: Intel CorporationInventors: Altug Koker, Joydeep Ray, Ben Ashbaugh, Jonathan Pearce, Abhishek Appu, Vasanth Ranganathan, Lakshminarayanan Striramassarma, Elmoustapha Ould-Ahmed-Vall, Aravindh Anantaraman, Valentin Andrei, Nicolas Galoppo Von Borries, Varghese George, Yoav Harel, Arthur Hunter, Jr., Brent Insko, Scott Janus, Pattabhiraman K, Mike Macpherson, Subramaniam Maiyuran, Marian Alin Petre, Murali Ramadoss, Shailesh Shah, Kamal Sinha, Prasoonkumar Surti, Vikranth Vemulapalli
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Patent number: 11606152Abstract: Channel predictive behavior and fault analysis may be provided. A forward time value may be determined comprising a time a forward signal takes to travel from a transmitter over a channel to the receiver. Next, a reflected time value may be determined comprising a time a reflected signal takes to travel to the receiver. The reflected signal may be associated with the forward signal. A discontinuity may then be determined to exist on the channel based on the forward time value and the reflected time value. The reflected signal may be caused by the discontinuity and a high impedance or low impedance at the transmitter present after the forward signal is sent.Type: GrantFiled: June 8, 2021Date of Patent: March 14, 2023Assignee: Cisco Technology, Inc.Inventors: Amendra Koul, David Nozadze, Mike Sapozhnikov, Joel Goergen, Arnav Shailesh Shah
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Publication number: 20220393776Abstract: Channel predictive behavior and fault analysis may be provided. A forward time value may be determined comprising a time a forward signal takes to travel from a transmitter over a channel to the receiver. Next, a reflected time value may be determined comprising a time a reflected signal takes to travel to the receiver. The reflected signal may be associated with the forward signal. A discontinuity may then be determined to exist on the channel based on the forward time value and the reflected time value. The reflected signal may be caused by the discontinuity and a high impedance or low impedance at the transmitter present after the forward signal is sent.Type: ApplicationFiled: June 8, 2021Publication date: December 8, 2022Applicant: Cisco Technology, Inc.Inventors: Amendra Koul, David Nozadze, Mike Sapozhnikov, Joel Goergen, Arnav Shailesh Shah
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Publication number: 20220261347Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.Type: ApplicationFiled: April 28, 2022Publication date: August 18, 2022Applicant: Intel CorporationInventors: Altug Koker, Joydeep Ray, Ben Ashbaugh, Jonathan Pearce, Abhishek Appu, Vasanth Ranganathan, Lakshminarayanan Striramassarma, Elmoustapha Ould-Ahmed-Vall, Aravindh Anantaraman, Valentin Andrei, Nicolas Galoppo Von Borries, Varghese George, Yoav Harel, Arthur Hunter,, JR., Brent Insko, Scott Janus, Pattabhiraman K, Mike Macpherson, Subramaniam Maiyuran, Marian Alin Petre, Murali Ramadoss, Shailesh Shah, Kamal Sinha, Prasoonkumar Surti, Vikranth Vemulapalli
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Publication number: 20220179787Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.Type: ApplicationFiled: March 14, 2020Publication date: June 9, 2022Applicant: Intel CorporationInventors: Altug Koker, Joydeep Ray, Ben Ashbaugh, Jonathan Pearce, Abhishek Appu, Vasanth Ranganathan, Lakshminarayanan Striramassarma, Elmoustapha Ould-Ahmed-Vall, Aravindh Anantaraman, Valentin Andrei, Nicolas Galoppo Von Borries, Varghese George, Yoav Harel, Arthur Hunter, Jr., Brent Insko, Scott Janus, Pattabhiraman K, Mike Macpherson, Subramaniam Maiyuran, Marian Alin Petre, Murali Ramadoss, Shailesh Shah, Kamal Sinha, Prasoonkumar Surti, Vikranth Vemulapalli