Abstract: A method of forming non-spherically shaped solder interconnects, preferably conical, for attachment of electronic components in an electronic module. Preferably, the solder interconnects of the present invention are cone shaped and comprise of depositing a first solder followed by a second solder having a lower reflow temperature than the first solder. Warm placement of the electronic component at a somewhat elevated temperature than room temperature but less than the solder reflow temperature reduces the force required during placement of a semiconductor chip to a substrate. After warm placement, reflow of the module occurs at the lower reflow temperature of the second solder. The conical shape of the solder interconnects are formed by a heated coining die which may also coin a portion of the interconnects with flat surfaces for stand-offs.

Abstract: This invention relates to a solder structure which provides enhanced fatigue life properties when used to bond substrates particularly at the second level such as BGA and CGA interconnections. The solder structure is preferably a sphere or column and has a metal layer wettable by solder and the structure is used to make solder connections in electronic components such as joining an electronic module such as a chip connected to a MLC which module is connected to a circuit board. The solder structure preferably has an overcoat of solder on the metal layer to provide a passivation coating to the metal layer to keep it clean from oxidation and corrosion and also provide a wettable surface for attachment of the solder structure to solder on the pads of the substrate being bonded.

Abstract: A copper-based paste is disclosed for filling vias in, and forming conductive surface patterns on, ceramic substrate packages for semiconductor chip devices. The paste contains copper aluminate powder in proper particle size and weight proportion to achieve grain size and shrinkage control of the via and thick film copper produced by sintering. The shrinkage of the copper material during sintering is closely matched to that of the ceramic substrate.

Abstract: A socketable ball grid array structure is disclosed which comprises mechanically rigid (compared to solder alloys) balls coated with noble contact metals joined to the chip carrier terminals by means of a novel electrically conducting adhesive. Because of the nature of the filler that includes conducting particles with a fusible coating and the appropriate selection of the polymer resin used in the adhesive, the balls are attached to the module in a compliant and resilient manner while leaving the majority of the bottom surface of the balls pristine. The array of balls can therefore be plugged into mating sockets in a printed circuit board forming a demountable contact. This facilitates easy removal of the socketable BGA from a board for repair or upgrade purposes as well as allows ease of plugging and unplugging of these BGA's into test and burn-in boards.

Abstract: An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 .mu.m thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer includes of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 .mu.m for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.

Abstract: A device and method for enabling the reworkability of an integrated circuit. The device includes a wirebond chip having a bottom surface and a carrier substrate having a first surface and a second surface. The first surface and second surface of the carrier substrate are electrically connected through a series of vias. A bonding agent is used to mechanically attach the wirebond chip to the carrier substrate in addition to wirebonds for electrically connecting the wirebond chip to the substrate. The substrate is attached to a multi-chip module (MCM) by ball grid array (BGA) or controlled collapse chip connection (C4) attaching process.

Abstract: A method for preforming electrochemical processes requiring the application of electricity on features of a substrate includes shorting out the features using a shorting layer across connectors to which the features a in electrical communication. Electricity is then applied and the process is performed.

Abstract: A method and apparatus is provided for forming an elongated solder joint between two soldered substrates of an electronic module by applying a controlled separating force between the two soldered substrates during and/or after heating of the module. The solder joints are plasticized, preferably to the molten state above the liquidus temperature, and are thereby stretched and the module is then cooled to solidify the stretched joints. An apparatus and method are provided which preferably uses a vacuum device as the separating force to stretch the existing solder joints to the desired solder height and configuration which is preferably an hour-glass shape.

Abstract: A semi-conductor packaging structure and a method to reduce the seal strain of the package are disclosed. The structure comprises a cap, substrate, seal and the cap and substrate have a predetermined TCE mismatch. The TCE mismatch between the cap and substrate is predetermined to minimize the seal strain during power-on and power-off use conditions. Preferably, the device has a substrate comprises a ceramic material, a cap with a thermal conductivity of at least about 100 W/m-K. A method of selecting a cap material is disclosed.

Abstract: A method and apparatus are provided for forming an elongated solder joint between two soldered substrates of an electronic module or an electronic module in the process of being fabricated by using expandable solder bump means disposed between the substrates. The expandable solder bumps means comprise solder having a higher reflow temperature than the solder used to join the substrates and expansion means such as a compressed spring encased within the solder and are activated (expanded) by reflowing at a higher temperature than the melting point temperature of the solder joints.

Abstract: A device is provided for stretching solder interconnection joints between two substrates of an electronic module. The device employs an expandable metal to exert a separating (stretching) force to the two substrates whereby a lifting rod attached to a clamping bridge is cause to move upwards by expansion of the expandable metal raising a first substrate clamped thereto. A lifting bridge in connection with the clamping bridge is caused to move downward to maintain the lifting bridge in contact with the second substrate being interconnected to the first substrate.

Abstract: A method is described for forming solder mounds for attachment to electronic devices. The solder mounds are preferably in the form of columns and comprise a first solder portion and a second solder portion with the two solder portions having different melting points. The solder columns are preferably formed using an injection molding device. The method is directed to the use of a single column mold to form the multi-solder column. In one embodiment, deformable material is used to partially block a portion of the through opening of the mold during a first solder injection process. The deformable material is then removed and the remainder of the through openings of the mold filled with a second molten solder. The multi-solder column is then electrically connected to a substrate by reflowing.

Abstract: A method of performing electrochemistry processes on features and connectors of a substrate includes the application of a shorting layer across the connectors which are in electrical contact with the features, thereby shorting the features and creating an assemblage for which electricity is applied.

Abstract: A copper-based paste is disclosed for filling vias in, and forming conductive surface patterns on, ceramic substrate packages for semiconductor chip devices. The paste contains copper aluminate powder in proper particle size and weight proportion to achieve grain size and shrinkage control of the via and thick film copper produced by sintering. The shrinkage of the copper material during sintering is closely matched to that of the ceramic substrate.

Abstract: Thin film capacitors are formed by a multi-level dry processing method that includes simultaneous ablation of via openings through both the dielectric and the metal electrode layers of a capacitor. Preferably, the dielectric films are formed of barium strontium titanate and the metal electrode layers are formed of platinum. The present invention overcomes the problems associated with the use of strong etchants to sequentially form separate via openings through the electrode and dielectric layers, prevents the potential for delamination of the respective layers during wet etching and the possible undesirable effects of etching solutions on substrate materials.

Abstract: The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

Abstract: Vias are formed in a dielectric film overlying an electrode layer by sweeping a laser beam over the area in which the via is to be formed. In particular, a Nd:YAG laser, producing a beam of light having a 266 nm wave length, effectively ablates a barium strontium titanate dielectric film, without adversely affecting an underlying platinum electrode. The present invention overcomes the problem of wet chemical etching of dielectric films to form vias. Wet chemical etching often requires etchants that adversely affect the underlying metal electrode and typically require the use of environmentally undesirable chemicals.

Abstract: Disclosed is a method of selectively depositing a metallic layer on a metallic feature on a ceramic substrate. The metallic layer preferably may be elemental nickel particles, elemental copper particles, a mixture of copper and nickel particles, or copper/nickel alloy particles. The metallic layer is deposited as a paste mixture which includes the metallic particles and a binder material. Through a subsequent heating step, the metallic layer tightly bonds to the metallic feature but only loosely bonds to the ceramic substrate. Thereafter, an ultrasonic treatment is applied to remove the loosely adhered metallic layer on the ceramic substrate. The metallic layer on the metallic feature, being tightly bonded, is not removed by the ultrasonic treatment.

Abstract: A semi-conductor packaging structure and a method to reduce the seal strain of the package are disclosed. The structure comprises a cap, substrate, seal and the cap and substrate have a predetermined TCE mismatch. The TCE mismatch between the cap and substrate is predetermined to minimize the seal strain during power-on and power-off use conditions. Preferably, the device has a substrate comprises a ceramic material, a cap with a thermal conductivity of at least about 100 W/m-K. A method of selecting a cap material is disclosed.

Abstract: The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.