Abstract: To protect memory cards, such as SD type cards, and similar devices from Electrostatic Discharge (ESD), the input pads of the device include points along their edges that are aligned with correspond points on a conductive frame structure mounted adjacent the input pad to form a spark gap. The input pads are connected to a memory controller or other ASIC over signal lines that include a diode located between the input pad and the ASIC and a resistance located between the input pad and the diode. The resistance and diode are selected such that an ESD event at an input pad triggers a discharge across the spark gap before it is transmitted on to the ASIC, while also allowing a high data rate for signals along the signal line.

Abstract: Memory cards having a nano card form factor configured according to different card standards. The nano card have a pair of opposed surfaces having a length and width of a nano SIM card in which a first group of interface pads on one of the opposed surfaces configured to mate with contact pins of a host device card slot operating per a PCIe memory card standard and a second group of interface pads configured to mate with contact pins of a host device card slot operating per a second memory card standard different than the PCIe memory card standard. The nano cards have patterns of pads allowing for vertical and horizontal insertion to a host device card slot being backward compatible with legacy host device card slots.

Abstract: To protect memory cards, such as SD type cards, and similar devices from Electrostatic Discharge (ESD), the input pads of the device include points along their edges that are aligned with correspond points on a conductive frame structure mounted adjacent the input pad to form a spark gap. The input pads are connected to a memory controller or other ASIC over signal lines that include a diode located between the input pad and the ASIC and a resistance located between the input pad and the diode. The resistance and diode are selected such that an ESD event at an input pad triggers a discharge across the spark gap before it is transmitted on to the ASIC, while also allowing a high data rate for signals along the signal line.

Abstract: Memory cards for example having a nano card form factor configured according to different card standards. The nano cards have patterns of pads allowing for vertical and horizontal insertion to a host device card slot, while being backward compatible with legacy host device card slots.

Abstract: A storage device comprises a controller, such as an ASIC controller, and one or more NAND flash memory devices. The controller comprises a differential receiver and a delay locked loop circuit. During read and write operations, the controller is configured to vary a delay of a data strobe signal by an interval across a width of a data window using the delay locked loop circuit, and to compare a write pattern to a read pattern for each delayed interval to determine the timing margins of the storage device. During read and write operations, the controller is further configured to apply a reference voltage to a host interface or a memory interface, increment and decrement the reference voltage by a set value, and compare a write pattern to a read pattern for each varied reference voltage value to determine the voltage margins of the storage device.

Abstract: A storage device comprises a controller, such as an ASIC controller, and one or more NAND flash memory devices. The controller comprises a differential receiver and a delay locked loop circuit. During read and write operations, the controller is configured to vary a delay of a data strobe signal by an interval across a width of a data window using the delay locked loop circuit, and to compare a write pattern to a read pattern for each delayed interval to determine the timing margins of the storage device. During read and write operations, the controller is further configured to apply a reference voltage to a host interface or a memory interface, increment and decrement the reference voltage by a set value, and compare a write pattern to a read pattern for each varied reference voltage value to determine the voltage margins of the storage device.

Abstract: A ?SD card is disclosed including an arrangement of interface pins enabling the ?SD card to be used in a combination connector having a slot configured to receive both ?SD cards and SIM cards. In examples, the ?SD card may include multiple rows and/or columns of interface pins configured at positions such that, when the ?SD card is inserted into a multi-card connector, the positions of the ?SD card interface pins do not overlap with the positions of SIM card contacts in the connector.

Abstract: System and method for dynamic termination control to enable use of an increased number of memory modules on a single channel. In some embodiments, six or eight DIMMs are coupled to a single channel. The dynamic termination scheme can include configurations for input bus termination (IBT) on each of the memory modules for the address bus/command bus and configurations for on-die termination (ODT) one each of the memory modules for the data bus.

Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.

Abstract: A non-source-synchronous system may include a clock-sending device and a clock-receiving device that communicate via a communications bus. The clock-sending device and the clock-receiving device may perform a tuning operation, in which the clock-receiving device sends one or more data signals on one or more data lines of the communications bus to the clock-sending device. The clock-sending device may delay its internal clock signal by an amount based on the one or more data signals. The clock-sending device may then perform sampling of data signals received from the clock-receiving device based on the tuning operation. The tuning operation may be performed in accordance with SDR or DDR, and thus allow for SDR or DDR communication with optimal sampling for systems that do not use a data strobe.

Abstract: System and method for dynamic termination control to enable use of an increased number of memory modules on a single channel. In some embodiments, six or eight DIMMs are coupled to a single channel. The dynamic termination scheme can include configurations for input bus termination (IBT) on each of the memory modules for the address bus/command bus and configurations for on-die termination (ODT) one each of the memory modules for the data bus.