Abstract: A self-aligned metal field effect transistor is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar.

Abstract: A self-aligned metal process is described which achieves self-aligned metal silicon contacts and micron-to-submicron contact-to-contact and metal-to-metal spacing by use of the pattern of dielectric material having a thickness in the order of a micron or less. The pattern of recessed oxide isolation to device area is also self-aligned by this process. The process results in substantially planar integrated circuit structure. The process is applicable to either a bipolar integrated circuit either bipolar or MOS field effect transistor integrated circuits.

Abstract: A process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistors. The insulation between the contacts and the metal is dielectric material having a thickness dimension about a micron or less. The structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the layer by reactive ion etching which results in the structure having horizontal surfaces and vertical surfaces. The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the horizontal surfaces and vertical surfaces.

Abstract: A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing in the Integrated Injection Logic (I.sup.2 L) technology. The method involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. The first insulating layer is removed in areas designated to contain integrated injection logic devices. A layer of highly doped polycrystalline silicon is formed thereover. The conductivity of the polycrystalline silicon is opposite to that of the silicon body. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are formed in areas designated to be the base of the lateral injector transistor of the integrated circuit.

Abstract: A non-volatile read mostly memory cell in a monocrystalline semiconductor body wherein the sensing of the information is achieved by measuring the substrate current.

Abstract: A process for forming holes with precisely controlled dimension and position in monocrystalline silicon wafers wherein the holes are fabricated with vertical sides. In the preferred process, both sides of the silicon body are masked, opposite registered openings made in the masking layers, an impurity introduced through the openings into the body forming low resistivity regions, the body anodically etched through the openings until a porous silicon region is formed completely through the body, and subsequently removing the resultant porous silicon region with a silicon etchant.

Abstract: A semiconductor device has a heavily doped semiconductor substrate with a lightly doped epitaxial layer overlying a surface of the substrate and of the same conductivity type as the substrate. Electrically insulating barriers extend from at least the surface of the epitaxial layer into the substrate so as to electrically isolate non-common areas of each surface leakage sensitive device within the epitaxial layer from the non-common areas of adjacent surface leakage sensitive devices.