Patents by Inventor Shakul TANDON
Shakul TANDON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240004310Abstract: Embodiments disclosed herein include semiconductor die with overlay marks, electronic devices that include semiconductor dies with overlay marks, and methods of measuring overlay. In one embodiment, a semiconductor die includes multiple overlay marks, including a first overlay mark and a second overlay mark. The first overlay mark is at a first position on the semiconductor die and includes a first set of patterns with a first orientation. The second overlay mark is at a second position on the semiconductor die and includes a second set of patterns with a second orientation. The first position of the first mark and the second position of the second mark are non-overlapping. In addition, the first orientation of the patterns in the first mark is substantially orthogonal to the second orientation of the patterns in the second mark.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: William Blanton, Deepak Selvanathan, Shakul Tandon, Martin N. Weiss
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Publication number: 20230205104Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to using full stack overlay cell (FSOL) targets within lithography masks and on fabricated layers of a substrate in order to align or to assess the alignment of fabricated layers of the substrate during the substrate manufacturing process. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 24, 2021Publication date: June 29, 2023Inventor: Shakul TANDON
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Publication number: 20230194997Abstract: Reticles, line feature patterns, and methods are described related to improving overlay margins in reticle stitching applications. A first reticle to expose a first field includes a first portion of a line feature. The first portion has a pattern inclusive of one or more pattern features. The first reticle or a second reticle to expose a second field adjacent the first filed includes a second portion of the line feature. The second portion has an inverse pattern relative to the first pattern such that, when the first and inverse patterns are overlaid, a continuous merged region is formed.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Mark Phillips, Shakul Tandon
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Publication number: 20230197638Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for a barrier that surrounds one or more dies which are electrically coupled with one or more electrical connections on a wafer. The barrier may be a hermetic barrier that is formed on a wafer prior to singulation to prevent moisture intrusion from a side of the wafer that may compromise the one or more electrical connections. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Mohammad Enamul KABIR, Keith ZAWADZKI, Shakul TANDON, Christopher M. PELTO, John Kevin TAYLOR, Babita DHAYAL
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Patent number: 11581162Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.Type: GrantFiled: July 29, 2021Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Shakul Tandon, Mark C. Phillips, Shem O. Ogadhoh, John A. Swanson
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Publication number: 20210358713Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.Type: ApplicationFiled: July 29, 2021Publication date: November 18, 2021Inventors: Shakul TANDON, Mark C. PHILLIPS, Shem O. OGADHOH, John A. SWANSON
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Patent number: 11107658Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.Type: GrantFiled: September 30, 2016Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Shakul Tandon, Mark C. Phillips, Shem O. Ogadhoh, John A. Swanson
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Patent number: 10395883Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction and having a pitch. Each opening of the first column of openings has a dimension in the first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The second column of openings has the pitch. Each opening of the second column of openings has the dimension in the first direction. A scan direction of the BAA is along a second direction orthogonal to the first direction. The openings of the first column of openings overlap with the openings of the second column of openings by at least 5% but less than 50% of the dimension in the first direction when scanned along the second direction.Type: GrantFiled: March 31, 2016Date of Patent: August 27, 2019Assignee: Intel CorporationInventors: Shakul Tandon, Mark C. Phillips, Gabriele Canzi
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Patent number: 10338474Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. Particular embodiments are directed to implementation of an underlying absorbing and/or conducting layer for ebeam direct write (EBDW) lithography.Type: GrantFiled: June 18, 2015Date of Patent: July 2, 2019Assignee: Intel CorporationInventors: Shakul Tandon, Yan A. Borodovsky, Charles H. Wallace, Paul A. Nyhus
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Publication number: 20190164723Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a method of forming a pattern for a semiconductor structure includes forming a pattern of parallel lines above a substrate. The method also includes aligning the substrate in an e-beam tool to provide the pattern of parallel lines parallel with a scan direction of the e-beam tool. The e-beam tool includes a column having a blanker aperture array (BAA) with a staggered pair of columns of openings along an array direction orthogonal to the scan direction. The method also includes forming a pattern of cuts or vias in or above the pattern of parallel lines to provide line breaks for the pattern of parallel lines by scanning the substrate along the scan direction. A cumulative current through the column has a non-zero and substantially uniform cumulative current value throughout the scanning.Type: ApplicationFiled: September 30, 2016Publication date: May 30, 2019Inventors: Shakul TANDON, Mark C. PHILLIPS, Shem O. OGADHOH, John A. SWANSON
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Publication number: 20190013175Abstract: Lithographic apparatuses suitable for complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction and having a pitch. Each opening of the first column of openings has a dimension in the first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The second column of openings has the pitch. Each opening of the second column of openings has the dimension in the first direction. A scan direction of the BAA is along a second direction orthogonal to the first direction. The openings of the first column of openings overlap with the openings of the second column of openings by at least 5% but less than 50% of the dimension in the first direction when scanned along the second direction.Type: ApplicationFiled: March 31, 2016Publication date: January 10, 2019Inventors: Shakul TANDON, Mark C. PHILLIPS, Gabriele CANZI
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Publication number: 20170338105Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. Particular embodiments are directed to implementation of an underlying absorbing and/or conducting layer for ebeam direct write (EBDW) lithography.Type: ApplicationFiled: June 18, 2015Publication date: November 23, 2017Inventors: Shakul TANDON, Yan A. BORODOVSKY, Charles H. WALLACE, Paul A. NYHUS