Abstract: An apparatus and method for generating scan chain connections for an integrated circuit (IC) in order to perform scan diagnosis of a manufactured IC chip, in which the scan chain connections are determined using functional path information among the flip flops of the IC design corresponding to the IC chip. A plurality of flip flops included in the IC is grouped into at least a first group and a second group based on the functional path information among the flip flops. At least one scan chain is generated from at least a portion of the flip flops in the first group. At least one scan chain is generated from at least a portion of the flip flops in the second group.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: State retention cells of a test circuit embedded in an electrical circuit are interconnected to form one or more scan chains. The scan chains are interconnected so that unknown states, or X-states, are shifted through the scan chains in an order other than the order in which the states were captured by the state retention cells of the scan chain. Such reordering of response states in individual scan chains may be used to align the X-states across multiple scan chains to achieve higher test compression scan register circuit testing.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: A method and system for test vector selection in statistical volume diagnosis using failed test data is disclosed. A computer-implemented method receives failures representing defects detected by an integrated circuit testing apparatus from a plurality of integrated circuits. Each of the plurality of integrated circuits is tested with a set of test vectors generated by the integrated circuit testing apparatus, and each of the plurality of failures is associated with a failed test vector. Using a first ranking scheme, each of the failures is given a rank and the corresponding failed test vector in each of the plurality of integrated circuits is annotated with the rank. The annotated failed test vectors are grouped using a grouping scheme, and each of the groups is given a group rank. A first group of failed test vectors is selected based on the group rank and diagnostics is run on the first group of failed test vectors.

Abstract: An integrated circuit is provided that comprises a power switch that includes a control terminal and that is coupled between a power source node and a power sink node; first data storage circuit includes a data storage input and a data storage output, wherein the data storage output is coupled to the power switch control terminal; and a second data storage circuit includes a data storage input and a data storage output, wherein the data storage input is coupled to the power sink node.

Abstract: State retention cells of a test circuit embedded in an electrical circuit are interconnected to form one or more scan chains. The scan chains are interconnected so that unknown states, or X-states, are shifted through the scan chains in an order other than the order in which the states were captured by the state retention cells of the scan chain. Such reordering of response states in individual scan chains may be used to align the X-states across multiple scan chains to achieve higher test compression scan register circuit testing.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: A method and system for test vector selection in statistical volume diagnosis using failed test data is disclosed. A computer-implemented method receives failures representing defects detected by an integrated circuit testing apparatus from a plurality of integrated circuits. Each of the plurality of integrated circuits is tested with a set of test vectors generated by the integrated circuit testing apparatus, and each of the plurality of failures is associated with a failed test vector. Using a first ranking scheme, each of the failures is given a rank and the corresponding failed test vector in each of the plurality of integrated circuits is annotated with the rank. The annotated failed test vectors are grouped using a grouping scheme, and each of the groups is given a group rank. A first group of failed test vectors is selected based on the group rank and diagnostics is run on the first group of tailed test vectors.