Patents by Inventor Shalini Gupta

Shalini Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230359540
    Abstract: Systems, methods, and storage media provided are useful in a computing environment receiving, modifying, and transforming service level information from database servers and entities in a hosted database environment. Multiple application programming interface (API) calls are made by a database observation system to request information for multiple service level indicators from database servers belonging to multiple different entities. Database observation system receives and aggregates the information for multiple service level indicators from each of the database servers belonging to multiple different entities. The database observation system provides, within a dashboard interface, the aggregated information for each of the multiple service level indicators, individual service level indicator scores, and aggregated service level indicator scores for each of the database servers for each of the multiple entities.
    Type: Application
    Filed: July 10, 2023
    Publication date: November 9, 2023
    Applicant: Cerner Innovation, Inc.
    Inventors: Naveen Kumar KN, Shamseer KK, Rohit Kumar, Pratyush Panigrahy, Eric Gold, Shalini Gupta, Thomas LeBlanc
  • Patent number: 11775410
    Abstract: Systems, methods, and storage media are provided that are useful in a computing environment for receiving, modifying, and transforming service level information from database servers and entities in a hosted database environment. Multiple application programming interface (API) calls are made by a database observation system to request information for multiple service level indicators from database servers belonging to multiple different entities. Database observation system receives and aggregates the information for multiple service level indicators from each of the database servers belonging to multiple different entities. The database observation system provides, within a dashboard interface, the aggregated information for each of the multiple service level indicators, individual service level indicator scores, and aggregated service level indicator scores for each of the database servers for each of the multiple entities.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: October 3, 2023
    Assignee: Cerner Innovation, Inc.
    Inventors: Naveen Kumar KN, Shamseer KK, Rohit Kumar, Pratyush Panigrahy, Eric Gold, Shalini Gupta, Thomas LeBlanc
  • Publication number: 20220350724
    Abstract: Systems, methods, and storage media are provided that are useful in a computing environment for receiving, modifying, and transforming service level information from database servers and entities in a hosted database environment. Multiple application programming interface (API) calls are made by a database observation system to request information for multiple service level indicators from database servers belonging to multiple different entities. Database observation system receives and aggregates the information for multiple service level indicators from each of the database servers belonging to multiple different entities. The database observation system provides, within a dashboard interface, the aggregated information for each of the multiple service level indicators, individual service level indicator scores, and aggregated service level indicator scores for each of the database servers for each of the multiple entities.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 3, 2022
    Inventors: Naveen Kumar KN, Shamseer KK, Rohit Kumar, Pratyush Panigrahy, Eric Gold, Shalini Gupta, Thomas LeBlanc
  • Patent number: 11100087
    Abstract: A system to tokenize values may include a processing unit; a storage device comprising instructions, which when executed by the processing unit, configure the processing unit to: receive a data item with an original value from a first storage system; store the data item in a staging table; transform the original value of the data item in the staging table to a changed value based on a stored rule; store a mapping between the original value and the changed value in a library table; and transmit the library table to a second storage system configured to update a database table at the second storage system based on the library table.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: August 24, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Shalini Gupta, Dharmesh Kumar, Elke Bregler, Rick Foucht, Navneet Saraogi, Frederic Huet, Ralph Yost, Gangaram Kanumuri
  • Patent number: 10985243
    Abstract: A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: April 20, 2021
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Josephine Bea Chang, Eric J. Stewart, Ken Alfred Nagamatsu, Robert S. Howell, Shalini Gupta
  • Patent number: 10976227
    Abstract: The present subject matter describes system (100) for magnetic enrichment of magnetically marked analytes. The system has capture chip (102) comprising a sample chamber (104) for holding sample having magnetically marked analytes, and a recovery chamber (106) connected to the sample chamber by a channel (202). The volume of recovery chamber is smaller than volume of sample chamber (104). The system has magnetic arrangement (108) comprising a set of magnets (110) in which each two adjacent magnets have opposite polarities facing sample chamber. Set of magnets has dimensions that at least conform to coverage area of sample chamber. The magnetic arrangement also has at least one recovery magnet (112) having dimensions conforming to coverage area of recovery chamber and on alignment, the at least one recovery magnet (112) is at a distance farthest away from the recovery chamber. The system has a linear positioner (114) for moving the magnetic arrangement.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 13, 2021
    Assignee: INDIAN INSTITUTE OF TECHNOLOGY DELHI
    Inventors: Ravikrishnan Elangovan, Vivekanandan Perumal, Shalini Gupta, Saurabh Singh, Mohita Upadhyay
  • Patent number: 10969388
    Abstract: The present invention relates to a membrane based assay method, device and kit for rapid detection and/or quantification of endotoxins in aqueous solutions and test samples. The kit as per the present invention comprises lipopolysaccharide (LPS) affinity ligand conjugated with gold nanoparticles (GNPs); a membrane device comprising an endotoxin affinity membrane positioned parallelly to one or more layer(s) of a hydrophilic material, which are optionally secured in an enclosure; and optionally comprising an indicator chart for quantification of endotoxins in the sample. The method comprises placing the sample suspected of endotoxin contamination on a surface of a membrane comprised in a membrane device; placing once or more a suspension of LPS-affinity ligand conjugated with GNPs over the same area as the sample placed and detecting the presence of endotoxin if the colour signal appears and based on its intensity quantifying the endotoxin levels.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: April 6, 2021
    Assignee: NanoDx Healthcare Pvt. Ltd.
    Inventors: Shalini Gupta, Venkataraman Sritharan, Prasanta Kalita
  • Patent number: 10854600
    Abstract: A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 1, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Justin Andrew Parke, Eric J. Stewart, Robert S. Howell, Howell George Henry, Bettina Nechay, Harlan Carl Cramer, Matthew Russell King, Shalini Gupta, Ronald G. Freitag, Karen Marie Renaldo
  • Publication number: 20200373384
    Abstract: A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: JOSEPHINE BEA CHANG, ERIC J. STEWART, KEN ALFRED NAGAMATSU, ROBERT S. HOWELL, SHALINI GUPTA
  • Publication number: 20200341965
    Abstract: A system to tokenize values may include a processing unit; a storage device comprising instructions, which when executed by the processing unit, configure the processing unit to: receive a data item with an original value from a first storage system; store the data item in a staging table; transform the original value of the data item in the staging table to a changed value based on a stored rule; store a mapping between the original value and the changed value in a library table; and transmit the library table to a second storage system configured to update a database table at the second storage system based on the library table.
    Type: Application
    Filed: April 26, 2019
    Publication date: October 29, 2020
    Inventors: Shalini Gupta, Dharmesh Kumar, Elke Bregler, Rick Foucht, Navneet Saraogi, Frederic Huet, Ralph Yost, Gangaram Kanumuri
  • Patent number: 10784341
    Abstract: A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: September 22, 2020
    Assignee: NORTHROP GRUMNIAN SYSTEMS CORPORATION
    Inventors: Josephine Bea Chang, Eric J. Stewart, Ken Alfred Nagamatsu, Robert S. Howell, Shalini Gupta
  • Publication number: 20200235202
    Abstract: A transistor is provided that comprises a source region overlying a base structure, a drain region overlying the base structure, and a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region. The block of semiconducting material comprises a gate controlled region adjacent the source region, and a drain access region disposed between the gate controlled region and the drain region. The drain access region is formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.
    Type: Application
    Filed: January 21, 2019
    Publication date: July 23, 2020
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: JOSEPHINE BEA CHANG, ERIC J. STEWART, KEN ALFRED NAGAMATSU, ROBERT S. HOWELL, SHALINI GUPTA
  • Patent number: 10690662
    Abstract: The subject matter discloses systems and methods for magnetic capturing of rare cells from a liquid sample. The system includes a capture chip (104) having a longitudinal channel (208) comprising a first part (304) and a second part (306). The capture chip (104) has a capture well (302) near an end of the second part (306) closer to an interfacing region between the first part (304) and the second part (306). The system includes a first set (126) of multiple rows of magnets for the magnetic capturing of the rare cells in the first part (304) of the longitudinal channel (208), where a first row (132) of the first set (126) of multiple rows has magnets that span a length of the first part (304) of the longitudinal channel (208) and each subsequent row of the first set (126) of multiple rows has one magnet less than a previous row.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 23, 2020
    Assignee: INDIAN INSTITUTE OF TECHNOLOGY DELHI
    Inventors: Ravikrishnan Elangovan, Vivekanandan Perumal, Shalini Gupta, Saurabh Singh
  • Publication number: 20200013775
    Abstract: A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 9, 2020
    Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: JUSTIN ANDREW PARKE, ERIC J. STEWART, ROBERT S. HOWELL, HOWELL GEORGE HENRY, BETTINA NECHAY, HARLAN CARL CRAMER, MATTHEW RUSSELL KING, SHALINI GUPTA, RONALD G. FREITAG, KAREN MARIE RENALDO
  • Patent number: 10509479
    Abstract: An apparatus and method for gesture detection and recognition. The apparatus includes a processing element, a radar sensor, a depth sensor, and an optical sensor. The radar sensor, the depth sensor, and the optical sensor are coupled to the processing element, and the radar sensor, the depth sensor, and the optical sensor are configured for short range gesture detection and recognition. The processing element is further configured to detect and recognize a hand gesture based on data acquired with the radar sensor, the depth sensor, and the optical sensor.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 17, 2019
    Assignee: NVIDIA Corporation
    Inventors: Pavlo Molchanov, Shalini Gupta, Kihwan Kim, Kari Pulli
  • Patent number: 10481696
    Abstract: An apparatus and method for radar based gesture detection. The apparatus includes a processing element and a transmitter configured to transmit radar signals. The transmitter is coupled to the processing element. The apparatus further includes a plurality of receivers configured to receive radar signal reflections, where the plurality of receivers is coupled to the processing element. The transmitter and plurality of receivers are configured for short range radar and the processing element is configured to detect a hand gesture based on the radar signal reflections received by the plurality of receivers.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: November 19, 2019
    Assignee: Nvidia Corporation
    Inventors: Pavlo Molchanov, Shalini Gupta, Kihwan Kim, Kari Pulli
  • Patent number: 10468406
    Abstract: A circuit is provided that includes a castellated channel device that comprises a heterostructure overlying a substrate structure, a castellated channel device area formed in the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, and a three-sided castellated conductive gate contact that extends across the castellated channel device area. The three-sided gate contact substantially surrounds each ridge channel around their tops and their sides to overlap a channel interface of heterostructure of each of the plurality of ridge channels. The three-sided castellated conductive gate contact extends along at least a portion of a length of each ridge channel.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: November 5, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Justin Andrew Parke, Eric J. Stewart, Robert S. Howell, Howell George Henry, Bettina Nechay, Harlan Carl Cramer, Matthew Russell King, Shalini Gupta, Ronald G. Freitag, Karen Marie Renaldo
  • Patent number: 10325982
    Abstract: A transistor device comprises a base structure and a superlattice of conducting channels overlying the base structure. The superlattice of conducting channels includes source and drain access regions spaced-apart from each other, a ledge between and spaced-apart from the source and drain access regions, and source-side alternating multichannel ridges and trenches that extend from the source access region to the ledge, each ridge having a topside and opposing sidewalls that each extend from the ledge to the source access region. The transistor device includes gate metal that covers each ridge continuously from the ledge to the source access region, such that the gate metal completely covers the topside of the ridge and edges of the conducting channels that intersect the sidewalls of the ridge.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: June 18, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Josephine Chang, Ken Alfred Nagamatsu, Robert Samuel Howell, Shalini Gupta
  • Patent number: 10311589
    Abstract: One embodiment of the present invention sets forth a technique for estimating a head pose of a user. The technique includes acquiring depth data associated with a head of the user and initializing each particle included in a set of particles with a different candidate head pose. The technique further includes performing one or more optimization passes that include performing at least one iterative closest point (ICP) iteration for each particle and performing at least one particle swarm optimization (PSO) iteration. Each ICP iteration includes rendering the three-dimensional reference model based on the candidate head pose associated with the particle and comparing the three-dimensional reference model to the depth data. Each PSO iteration comprises updating a global best head pose associated with the set of particles and modifying at least one candidate head pose. The technique further includes modifying a shape of the three-dimensional reference model based on depth data.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: June 4, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Gregory P. Meyer, Shalini Gupta, Iuri Frosio, Nagilla Dikpal Reddy, Jan Kautz
  • Publication number: 20190079088
    Abstract: The present invention relates to a membrane based assay method, device and kit for rapid detection and/or quantification of endotoxins in aqueous solutions and test samples. The kit as per the present invention comprises lipopolysaccharide (LPS) affinity ligand conjugated with gold nanoparticles (GNPs); a membrane device comprising an endotoxin affinity membrane positioned parallelly to one or more layer(s) of a hydrophilic material, which are optionally secured in an enclosure; and optionally comprising an indicator chart for quantification of endotoxins in the sample. The method comprises placing the sample suspected of endotoxin contamination on a surface of a membrane comprised in a membrane device; placing once or more a suspension of LPS-affinity ligand conjugated with GNPs over the same area as the sample placed and detecting the presence of endotoxin if the colour signal appears and based on its intensity quantifying the endotoxin levels.
    Type: Application
    Filed: November 11, 2016
    Publication date: March 14, 2019
    Inventors: Shalini GUPTA, Venkataraman SRITHARAN, Prasanta KALITA