Patents by Inventor Shalini Pathak

Shalini Pathak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SCAN COMPRESSION THROUGH PIN DATA ENCODING
    Publication number: 20230375617
    Abstract: A method for testing a chip comprising receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Sandeep Jain, Shalini Pathak
  • Scan compression through pin data encoding
    Patent number: 11782092
    Abstract: A method for testing a chip comprising: receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: October 10, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Sandeep Jain, Shalini Pathak
  • Method and device for testing configuration memory cells in programmable logic devices (PLDS)
    Patent number: 7167404
    Abstract: A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage device for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row. The PLD may also include an output data storage device for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: January 23, 2007
    Assignee: STMicroelectronics Pvt Ltd.
    Inventors: Shalini Pathak, Parvesh Swami
  • Method and device for testing configuration memory cells in programmable logic devices (PLDS)
    Publication number: 20040015758
    Abstract: A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage device for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row. The PLD may also include an output data storage device for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.
    Type: Application
    Filed: May 13, 2003
    Publication date: January 22, 2004
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventors: Shalini Pathak, Parvesh Swami