Abstract: A method and system that enables concurrent event handler execution in a system management interrupt (SMI) and processor management interrupt (PMI)-based dispatch-execution framework to service an SMI or PMI event. A plurality of event handlers are loaded into a hidden memory space that is accessible to a hidden execution mode supported by each of a plurality of processors in a multiprocessor computer system but is not accessible to other operating modes of those processors. The event handlers are then dispatched to two or more processors in response to the hidden execution mode event and concurrently executed to service the event. Various embodiments include use of a single event handler to service the event, multiple event handlers that perform different tasks, and multiple event handler instances that concurrently perform a single task. The invention also provides a resource locking mechanism to prevent resource access conflicts.

Abstract: A novel processor architecture and algorithms are provided which improve non-volatile memory updates and increases processor performance in successive generations of processors. A new processor architecture is supported by a software model consisting of two new firmware layers and the legacy 32 bit basic input output system (BIOS) firmware. The new firmware layers consist of a Processor Abstraction Layer (PAL) and a System Abstraction Layer (SAL). The PAL and SAL have procedure calls which allow updates of the firmware components in the non-volatile memory of a system, e.g. non-volatile ROM. The present invention includes invoking a system abstraction layer update procedure to implement a new input binary into the non-volatile memory. An algorithm for the non-volatile memory includes selecting a lead processor to perform an update and using the system abstraction layer update procedure. The system abstraction layer update procedure is used to call an appropriate authentication routine.

Abstract: Prior to the initialization of system memory, a processor cache may be utilized as a random access memory to permit more complex initialization protocols. For example, both data and instruction caches may be utilized to perform software functions involving higher level programming languages at early initialization stages.

Abstract: In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.

Abstract: A boot routine is initialized in a computer by bootstrapping a volume top file (VTF) located in a first addressable location accessible upon the initializing of the boot routine and the volume top file bootstrapping a set of firmware modules.

Abstract: A method and system that enables concurrent event handler execution in a system management interrupt (SMI) and processor management interrupt (PMI)-based dispatch-execution framework to service an SMI or PMI event. A plurality of event handlers are loaded into a hidden memory space that is accessible to a hidden execution mode supported by each of a plurality of processors in a multiprocessor computer system but is not accessible to other operating modes of those processors. The event handlers are then dispatched to two or more processors in response to the hidden execution mode event and concurrently executed to service the event. Various embodiments include use of a single event handler to service the event, multiple event handlers that perform different tasks, and multiple event handler instances that concurrently perform a single task. The invention also provides a resource locking mechanism to prevent resource access conflicts.

Abstract: A method and apparatus for the dynamic inclusion or exclusion of initialization modules within the set of initialization modules designated as recovery initialization modules is described. When a BIOS system is updated through the inclusion of a new initialization module, the algorithm of the present invention dynamically determines if the initialization module is required for recovery. A firmware update utility evaluates new initiation modules to determine if they are designated as recovery or required by core recovery modules. If so, the new module is designated for recovery and stored to a fault-tolerant block within a recovery file volume. The firmware update utility of the present invention allows an initiation module to be automatically designated as recovery only when necessary. Initiation modules, designated as recovery, that subsequently are not required fro recovery may be omitted from the recovery set. Thus the collection of recovery initiation modules is minimized.

Abstract: A method for switching between a first mode and a second mode of a processor is provided. According to one embodiment of the invention, a computer system includes the processor coupled to a storage device storing a number of instructions. In response to a first interrupt, a first information is stored in the storage device for switching to processing in the first mode starting at a first of the number of instructions. In response to a second interrupt occurring subsequent to the storing of the first information, said processor switches from processing in the first mode to processing in the second mode. Also in response to the second interrupt, a second information is storm in the storage device for returning to processing in the first mode starting at a second of the number of instructions.