Patents by Inventor Shamanna M. Datta
Shamanna M. Datta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11861053Abstract: Techniques for tamper detection of a memory module having non-volatile memory devices resident on a printed circuit board (PCB) by circuitry of a controller also resident on the PCB. Examples include determining resistance values of a character pattern sprayed on a side of a cover facing the non-volatile memory devices using conductive ink following first and second boots of the memory module and asserting a bit of a register to indicate tampering of the memory modules based on a comparison of the resistance values. Tamper policy actions may be initiated based on detection of tampering.Type: GrantFiled: December 16, 2020Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Shamanna M. Datta, Asher M. Altman, John K. Grooms, Mohamed Arafa
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Patent number: 11379214Abstract: An interface is provided to update a firmware of a persistent memory module at runtime without restarting an operating system on the platform. The operating system initiates the firmware update by triggering a sleep state or by entering a soft reboot. The interface is capable of preserving the state of the platform for all memory modes that support volatile memory regions, persistent memory regions, or both, and reducing or eliminating the demand for access to memory during the firmware update. The persistent memory module is capable of updating the firmware responsive to a platform instruction generated using the interface, including preserving operational states for memory devices in all memory regions, including memory devices in volatile and persistent memory regions.Type: GrantFiled: March 29, 2019Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Murugasamy K. Nachimuthu, Mohan J. Kumar, Shamanna M. Datta
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Publication number: 20210103684Abstract: Techniques for tamper detection of a memory module having non-volatile memory devices resident on a printed circuit board (PCB) by circuitry of a controller also resident on the PCB. Examples include determining resistance values of a character pattern sprayed on a side of a cover facing the non-volatile memory devices using conductive ink following first and second boots of the memory module and asserting a bit of a register to indicate tampering of the memory modules based on a comparison of the resistance values. Tamper policy actions may be initiated based on detection of tampering.Type: ApplicationFiled: December 16, 2020Publication date: April 8, 2021Inventors: Shamanna M. DATTA, Asher M. ALTMAN, John K. GROOMS, Mohamed ARAFA
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Patent number: 10671416Abstract: Various embodiments are generally directed to the provision and use of various hardware and software components of a computing device to monitor the state of layered virtual machine (VM) monitoring software components. An apparatus includes a first processor element; and logic to receive an indication that a first timer has reached an end of a first period of time, monitor execution of a VMM (virtual machine monitor) watcher by a second processor element, determine whether the second processor element completes execution of the VMM watcher to verify integrity of a VMM before a second timer reaches an end of a second period of time, and transmit an indication of the determination to a computing device. Other embodiments are described and claimed.Type: GrantFiled: July 31, 2017Date of Patent: June 2, 2020Assignee: INTEL CORPORATIONInventors: Mahesh S. Natu, Shamanna M. Datta
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Patent number: 10671466Abstract: Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.Type: GrantFiled: September 18, 2017Date of Patent: June 2, 2020Assignee: Intel CorporationInventors: Shamanna M. Datta, Murugasamy K. Nachimuthu, Mahesh S. Natu
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Publication number: 20190243637Abstract: An interface is provided to update a firmware of a persistent memory module at runtime without restarting an operating system on the platform. The operating system initiates the firmware update by triggering a sleep state or by entering a soft reboot. The interface is capable of preserving the state of the platform for all memory modes that support volatile memory regions, persistent memory regions, or both, and reducing or eliminating the demand for access to memory during the firmware update. The persistent memory module is capable of updating the firmware responsive to a platform instruction generated using the interface, including preserving operational states for memory devices in all memory regions, including memory devices in volatile and persistent memory regions.Type: ApplicationFiled: March 29, 2019Publication date: August 8, 2019Inventors: Murugasamy K. NACHIMUTHU, Mohan J. KUMAR, Shamanna M. DATTA
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Patent number: 10303503Abstract: An apparatus and method for hardware protection of a virtual machine monitor (VMM) runtime integrity watcher is described. A set of one or more hardware range registers that protect a contiguous memory space that is to store the VMM runtime integrity watcher. The set of hardware range registers are to protect the VMM runtime integrity watcher from being modified when loaded into the contiguous memory space. The VMM runtime integrity watcher, when executed, performs an integrity check on a VMM during runtime of the VMM.Type: GrantFiled: February 14, 2017Date of Patent: May 28, 2019Assignee: Intel CorporationInventors: Shamanna M. Datta, Alberto J. Munoz, Mahesh S. Natu, Scott T. Durrant
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Patent number: 10169268Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.Type: GrantFiled: September 20, 2016Date of Patent: January 1, 2019Assignee: Intel CorporationInventors: Mahesh Natu, Thanunathan Rangarajan, Gautam Doshi, Shamanna M. Datta, Baskaran Ganesan, Mohan J. Kumar, Rajesh S. Parthasarathy, Frank Binns, Rajesh Nagaraja Murthy, Robert C. Swanson
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Publication number: 20180143923Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.Type: ApplicationFiled: January 17, 2018Publication date: May 24, 2018Inventors: Mahesh Natu, Thanunathan Rangarajan, Gautam Doshi, Shamanna M. Datta, Baskaran Ganesan, Mohan J. Kumar, Rajesh S. Parthasarathy, Frank Binns, Rajesh Nagaraja Murthy, Robert C. Swanson
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Publication number: 20180067794Abstract: Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.Type: ApplicationFiled: September 18, 2017Publication date: March 8, 2018Applicant: Intel CorporationInventors: Shamanna M. Datta, Murugasamy K. Nachimuthu, Mahesh S. Natu
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Publication number: 20170371689Abstract: Various embodiments are generally directed to the provision and use of various hardware and software components of a computing device to monitor the state of layered virtual machine (VM) monitoring software components. An apparatus includes a first processor element; and logic to receive an indication that a first timer has reached an end of a first period of time, monitor execution of a VMM (virtual machine monitor) watcher by a second processor element, determine whether the second processor element completes execution of the VMM watcher to verify integrity of a VMM before a second timer reaches an end of a second period of time, and transmit an indication of the determination to a computing device. Other embodiments are described and claimed.Type: ApplicationFiled: July 31, 2017Publication date: December 28, 2017Applicant: INTEL CORPORATIONInventors: MAHESH S. NATU, SHAMANNA M. DATTA
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Patent number: 9766963Abstract: Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.Type: GrantFiled: September 23, 2015Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Shamanna M. Datta, Murugasamy K. Nachimuthu, Mahesh S. Natu
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Publication number: 20170252170Abstract: An apparatus and method for hardware protection of a virtual machine monitor (VMM) runtime integrity watcher is described. A set of one or more hardware range registers that protect a contiguous memory space that is to store the VMM runtime integrity watcher. The set of hardware range registers are to protect the VMM runtime integrity watcher from being modified when loaded into the contiguous memory space. The VMM runtime integrity watcher, when executed, performs an integrity check on a VMM during runtime of the VMM.Type: ApplicationFiled: February 14, 2017Publication date: September 7, 2017Inventors: Shamanna M. Datta, Alberto J. Munoz, Mahesh S. Natu, Scott T. Durrant
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Patent number: 9720716Abstract: Various embodiments are generally directed to the provision and use of various hardware and software components of a computing device to monitor the state of layered virtual machine (VM) monitoring software components. An apparatus includes a first processor element; and logic to receive an indication that a first timer has reached an end of a first period of time, monitor execution of a VMM (virtual machine monitor) watcher by a second processor element, determine whether the second processor element completes execution of the VMM watcher to verify integrity of a VMM before a second timer reaches an end of a second period of time, and transmit an indication of the determination to a computing device. Other embodiments are described and claimed.Type: GrantFiled: March 12, 2013Date of Patent: August 1, 2017Assignee: INTEL CORPORATIONInventors: Mahesh S. Natu, Shamanna M. Datta
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Publication number: 20170083393Abstract: Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.Type: ApplicationFiled: September 23, 2015Publication date: March 23, 2017Applicant: INTEL CORPORATIONInventors: Shamanna M. Datta, Murugasamy K. Nachimuthu, Mahesh S. Natu
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Publication number: 20170062023Abstract: Apparatus, systems, and methods to implement boot operations in nonvolatile storage devices can include, in one example, a controller comprising logic to receive a power down instruction, record a timestamp associated with the power down instruction, and store the timestamp in a nonvolatile memory table communicatively coupled to the controller. Other examples are also disclosed and claimed.Type: ApplicationFiled: August 26, 2015Publication date: March 2, 2017Applicant: INTEL CORPORATIONInventors: Shamanna M. Datta, Richard P. Mangold, Mahesh S. Natu
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Patent number: 9566158Abstract: An apparatus and method for hardware protection of a virtual machine monitor (VMM) runtime integrity watcher is described. A set of one or more hardware range registers that protect a contiguous memory space that is to store the VMM runtime integrity watcher. The set of hardware range registers are to protect the VMM runtime integrity watcher from being modified when loaded into the contiguous memory space. The VMM runtime integrity watcher, when executed, performs an integrity check on a VMM during runtime of the VMM.Type: GrantFiled: December 31, 2011Date of Patent: February 14, 2017Assignee: Intel CorporationInventors: Shamanna M. Datta, Albert J. Munoz, Mahesh S. Natu, Scott T. Durrant
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Publication number: 20170010991Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.Type: ApplicationFiled: September 20, 2016Publication date: January 12, 2017Inventors: Mahesh Natu, Thanunathan Rangarajan, Gautam Doshi, Shamanna M. Datta, Baskaran Ganesan, Mohan J. Kumar, Rajesh S. Parthasarathy, Frank Binns, Rajesh Nagaraja Murthy, Robert C. Swanson
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Patent number: 9465647Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.Type: GrantFiled: October 8, 2013Date of Patent: October 11, 2016Assignee: Intel CorporationInventors: Mahesh Natu, Thanunathan Rangarajan, Gautam Doshi, Shamanna M. Datta, Baskaran Ganesan, Mohan J. Kumar, Rajesh S. Parthasarathy, Frank Binns, Rajesh Nagaraja Murthy, Robert C. Swanson
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Patent number: 9448867Abstract: A method is described that includes detecting that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of the system management program code again information that defines confines of the protection region. The method also includes raising an error signal in response to the detecting.Type: GrantFiled: December 31, 2011Date of Patent: September 20, 2016Assignee: Intel CorporationInventors: Shamanna M. Datta, Rajesh S. Parathasarathy, Mahesh S. Natu, Frank Binns, Mohan J. Kumar