Patents by Inventor Shams Khan

Shams Khan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11068888
    Abstract: A value-transfer payment system, having an electronic device, an operations center, a blockchain, a decentralized mesh networking, and an identification confidence-based system. The blockchain is associated to the decentralized mesh networking to define an immutable and decentralized platform that allows users to transfer funds. The electronic device is a computer device or a teller machine. The blockchain associated with the decentralized mesh networking is accessed via Internet with the computer device through a central website, mobile applications, or through third-party website/mobile applications or through the teller machine. The decentralized mesh networking has a plurality of nodes operatively associated to each other. The value-transfer payment system works in rural locations through the decentralized mesh networking, whereby the users are allowed for transfer the funds with or without the availability of traditional dial-up, broadband, or wireless Internet connectivity.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: July 20, 2021
    Assignee: Countia, LLC.
    Inventors: Ronell Levatte, Ryan Seay, Shams Khan
  • Patent number: 5062036
    Abstract: Instruction prefetching apparatus particularly adapted to executing an EXECUTE instruction specifiying a single subject instruction. The apparatus includes a first and second separately-controllable instruction syllable register and control apparatus. Under control of the control apparatus, the first instruction syllable register receives only the first syllable of the prefetched instruction; the second instruction syllable register receives all other syllables. The instruction syllable registers may be loaded either directly from memory or from a data register internal to the CPU. In the first case, the address of the instruction syllable to be prefetched is contained in a special instruction address register which is incremented each time an instruction syllable register is loaded. In the second case, the loading does not affect the value of the instruction address register.
    Type: Grant
    Filed: April 3, 1989
    Date of Patent: October 29, 1991
    Assignee: Wang Laboratories, Inc.
    Inventors: Arthur Barrow, Kin L. Cheung, Jeffrey W. Einarson, Shams A. Khan