Patents by Inventor Shamsul Abedin

Shamsul Abedin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11905814
    Abstract: A method for preparing a geothermal system involves preparing a wellbore that extends into an underground magma reservoir. Characteristics of the drilling process and the borehole are monitored to detect when the magma reservoir is reached, such that specially configured drilling operations can be performed to drill to a target depth within the magma reservoir.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: February 20, 2024
    Assignee: EnhancedGEO Holdings, LLC
    Inventors: Benjamin Chris Smith, James Michael Browning, Randall Howard Hornbaker, Kevin Martin Stone, Georgios Evangelatos, Shamsul Abedin Al-Tomal, Andrew Nguyen
  • Patent number: 11815984
    Abstract: A system level error detection and handling of the network IO in a multi-chip-package (MCP) die is provided. The error detection and handling mechanism conceived may be used between a system-on-chip (SoC) die and a different type of die, such as a die manufactured by a third-party (e.g., a high-bandwidth network IO die). To provide a timely indication in case of any part of the network is at fault, a control unit on the SoC die handles error detection on the network IO links using various indicators. After errors are detected, the control unit groups the errors into two categories: a link failure and a virtual channel failure. Such an error handling mechanism may consolidate the actions and provide consistency in hardware behavior.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventors: Tina C. Toupal, Shamsul Abedin
  • Publication number: 20220196936
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a bidirectional optical grating coupler that may be used for testing. A photonic apparatus includes a first layer with electro-optical circuitry that is optically coupled with a bidirectional optical grating coupler. A second layer is physically coupled with a first side of the first layer and includes a first light path to optically coupled with the bidirectional optical grating coupler. A third layer is physically coupled with a second side of the first layer opposite the first side of the first layer, and includes a second light path that optically couples with the bidirectional grating coupler. Operational testing of the electro-optical circuitry is based in part on light received or transmitted through the second light path. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Inventors: Kaveh HOSSEINI, Xiaoqian LI, Conor O'KEEFFE, Jing FANG, Kevin P. MA, Shamsul ABEDIN
  • Publication number: 20200174873
    Abstract: A system level error detection and handling of the network IO in a multi-chip-package (MCP) die is provided. The error detection and handling mechanism conceived may be used between a system-on-chip (SoC) die and a different type of die, such as a die manufactured by a third-party (e.g., a high-bandwidth network IO die). To provide a timely indication in case of any part of the network is at fault, a control unit on the SoC die handles error detection on the network IO links using various indicators. After errors are detected, the control unit groups the errors into two categories: a link failure and a virtual channel failure. Such an error handling mechanism may consolidate the actions and provide consistency in hardware behavior.
    Type: Application
    Filed: February 7, 2020
    Publication date: June 4, 2020
    Inventors: Tina C. Toupal, Shamsul Abedin
  • Publication number: 20070075753
    Abstract: A duty cycle measurement circuit and method of operation is described that is particularly well adapted for use in microelectronics devices. In one embodiment, the circuit the includes a clock signal selector to alternately select the high or the low phase of an input clock signal, a sweep circuit to sweep a timing parameter through a range, and a latch to compare the clock signal to the timing parameter and generate a result.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Rachael Parker, Mark Neidengard, Shamsul Abedin