Patents by Inventor Shan Cheng

Shan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250112195
    Abstract: A semiconductor device arrangement structure includes a carrier, semiconductor devices, and an adhesive layer. The semiconductor devices are separately disposed on the carrier, and each of the semiconductor devices includes an electrode. The adhesive layer is disposed between the carrier and the semiconductor devices, and the semiconductor devices are attached to the adhesive layer which is a continuous distributed single-layered structure. The adhesive layer includes unselected regions and a selected region, wherein the unselected regions are covered by the semiconductor devices respectively, and the selected region is not covered by the semiconductor devices. The adhesive layer further includes an indentation disposed on a surface of the selected region, and in a cross-sectional view or a top view, the contour of the indentation is a scaled copy of a contour of and the electrode, and the indentation has a depth less than that of the electrode.
    Type: Application
    Filed: October 1, 2024
    Publication date: April 3, 2025
    Inventors: Wen-Chien WU, Wei-Shan HU, Ching-Tai CHENG
  • Publication number: 20250103751
    Abstract: A computing circuit with a de-identified architecture, a data computing method, a data processing system, and a data de-identification method are provided. The computing circuit includes an arithmetic array and a de-identification circuit. The computing circuit may perform an accumulation operation on input data to generate accumulated data by the arithmetic array. The de-identification circuit has an analog offset error determined based on an analog physical unclonable function. The computing circuit may operate the accumulated data according to the analog offset error to generate de-identification data by the de-identification circuit. It can not only provide the analog offset error through the transistors in the de-identification circuit, but also be combined with obfuscated code settings to dynamically adjusting the degree of de-identification of data.
    Type: Application
    Filed: September 26, 2024
    Publication date: March 27, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Bo-Cheng Chiou, Chih-Sheng Lin, Tuo-Hung Hou, Chih-Ming Lai, Yun-Ting Ho, Shan-Ming Chang
  • Publication number: 20250102885
    Abstract: A switching mechanism is provided. The switching mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is movable relative to the fixed portion. The driving assembly is configured to drive the movable portion to move. The switching mechanism can further include a sensing assembly configured to detect the condition of the movable portion. The sensing assembly includes a first reference object and a first sensing member. The first sensing member corresponds to the first reference object, and the first reference object is adjacent to the first sensing member when the movable portion is in a first condition.
    Type: Application
    Filed: September 25, 2024
    Publication date: March 27, 2025
    Inventors: Pai-Jui CHENG, Shu-Shan CHEN, June-Yue HOU, Chuan-Min LEE
  • Patent number: 12261170
    Abstract: A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.
    Type: Grant
    Filed: June 29, 2023
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
  • Publication number: 20250092554
    Abstract: A release carrier structure includes a carrier layer, a first release layer, and a second release layer. A weight ratio of organic matter in the second release layer is greater than a weight ratio of organic matter in the first release layer.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 20, 2025
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Wei-Sheng Cheng, Yu-Chi Hsieh, Chia-Shan Chang
  • Publication number: 20250096254
    Abstract: A lithium battery positive material includes lithium nickel manganese oxide (LNMO) doped with copper, titanium, nitrogen, and carbon. In addition, a manufacturing method of the lithium battery positive material is also provided.
    Type: Application
    Filed: October 26, 2023
    Publication date: March 20, 2025
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Wei-Sheng Cheng, Chia-Shan Chang, Yu-Chi Hsieh
  • Publication number: 20250092555
    Abstract: A manufacturing method of a roughened copper foil includes the following steps. A copper foil is provided. An electrolytic process is performed to form a roughening layer on the copper foil. An electrolyte solution in the electrolysis process includes copper ions in a range from 0.1 g/L to 20 g/L, sulfate ions in a range from 30 g/L to 120 g/L, and a coordination compound in a range from 0.1 g/L to 10 g/L.
    Type: Application
    Filed: October 25, 2023
    Publication date: March 20, 2025
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Wei-Sheng Cheng, Yu-Chi Hsieh, Chia-Shan Chang
  • Publication number: 20250087082
    Abstract: Provided are a digital twinning method and system for a scene flow based on a dynamic trajectory flow, which belong to the field of traffic control. The method includes: extracting and identifying a target semantic trajectory with a detecting and tracking integrated multi-modal fusion and perception enhancement network; extracting road traffic semantics, so as to obtain a highly parameterized virtual road layout top view; obtaining a road layout traffic semantic grid encoding vector based on the virtual road layout top view; constructing a target coupling relation model; constructing a traffic force constraint model; constructing a long short term memory trajectory prediction network; predicting a motion trajectory of a target with the long short term memory trajectory prediction network, so as to obtain the predicted motion trajectory; and obtaining a digital twin of the scene flow based on trajectory extraction, semantic identification and the predicted motion trajectory.
    Type: Application
    Filed: March 22, 2023
    Publication date: March 13, 2025
    Inventors: Zhanwen LIU, Xing FAN, Shan LIN, Chao LI, Jun ZHAI, Yanming Fang, Songhua FAN, Zijian WANG, Nan YANG, Zhibiao XUE, Jin FAN, Juanru CHENG, Yuande JIANG, Litong ZHANG
  • Publication number: 20250073667
    Abstract: A complex ionic compound includes a carrier, a bridging agent, and an adsorbent. The bridging agent is grafted to the carrier, and the adsorbent is grafted to the bridging agent.
    Type: Application
    Filed: October 22, 2023
    Publication date: March 6, 2025
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Wei-Sheng Cheng, Chia-Shan Chang, Yu-lin Li
  • Publication number: 20250081529
    Abstract: Embodiments with present disclosure provides a gate-all-around FET device including extended bottom inner spacers. The extended bottom inner prevents the subsequently formed epitaxial source/drain region from volume loss and induces compressive strain in the channel region to prevent strain loss and channel resistance degradation.
    Type: Application
    Filed: March 1, 2024
    Publication date: March 6, 2025
    Inventors: Chien-Chia CHENG, Chih-Chiang CHANG, Ming-Hua YU, Chii-Horng LI, Chung-Ting KO, Sung-En LIN, Chih-Shan CHEN, De-Fang CHEN
  • Publication number: 20250081587
    Abstract: A semiconductor device includes a channel structure, extending along a first lateral direction, that is disposed over a substrate. The semiconductor device includes a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure. The semiconductor device includes an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure. The semiconductor device includes a first gate spacer and a second gate spacer each comprising a first portion disposed between the gate structure and the epitaxial structure along the first lateral direction. The semiconductor device includes an air gap interposed between the first portion of the first gate spacer and the first portion of the second gate spacer. The air gap exposes a second portion of the first gate spacer that extends in the first lateral direction.
    Type: Application
    Filed: November 14, 2024
    Publication date: March 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Hsiao Wen Lee, Yu-Shan Cheng, Ming-Ching Chang
  • Patent number: 12237017
    Abstract: A block erase method for a flash memory is provided. The block erase method is to perform block erase on a block with a predetermined block size. The block erase method includes: performing an erase verification on bytes byte-by-byte in the block when performing the block erase; checking an erase step of the byte when the byte does not pass the erase verification; when the erase step of the byte exceeds a predetermined threshold value, performing the block erase with a partitioned block smaller than the predetermined block size, and returning to an erase verification stage to perform the erase verification; and when the erase step of the bytes does not exceed the predetermined threshold value, continuing to perform the block erase with the predetermined block size, and returning to the erasure verification stage to continue to perform the erase verification.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: February 25, 2025
    Assignee: Winbond Electronics Corp.
    Inventors: Lung-Chi Cheng, Ying-Shan Kuo, Jun-Yao Huang, Ju-Chieh Cheng, Yu-Cheng Chuang
  • Publication number: 20250049585
    Abstract: The present disclosure provides a customized module-wise bra with both aesthetic, comfort, and functions assisting a post-mastectomy subject to wear the bra and correct any postural distortion arising from imbalance due to loss of weight from the mastectomized breast. Also provided herein is a method for fabricating the customized module-wise bra according to the anatomical/physical characteristics of the subject based on various 3D printing, 3D body scanning and ultrasonography techniques.
    Type: Application
    Filed: January 20, 2023
    Publication date: February 13, 2025
    Inventors: Gloria Lei YAO, Hing-leung CHAN, Erika Kit-shan NGAN, Kaoru Ting-fong LEUNG, Kain Hung-chiu WU, Jasmine Li CHI, Yammy Yan-yi CHENG
  • Patent number: 12225276
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a first holder, a fixed portion, a first driving assembly, and a first stopping assembly. The first holder is used for connecting to an optical element. The first holder is movable relative to the fixed portion. The first driving assembly is used for driving the first holder to move relative to the fixed portion. The first stopping assembly is used for restricting the movable range of the first holder relative to the fixed portion.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: February 11, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Hsiao-Hsin Hu, Shu-Shan Chen, Chao-Chang Hu, Pai-Jui Cheng, Chieh-An Chang
  • Patent number: 12224684
    Abstract: An optical element driving mechanism is provided in the present disclosure, including a fixed portion, a movable portion that is connected to an optical assembly, and a driving assembly that drives the movable portion to move relative to the fixed portion and includes a piezoelectric element. The piezoelectric element includes a piezoelectric unit, a guiding element, and a counterweight element. A first end of the guiding element is connected to the piezoelectric unit, and a second end is connected to the fixed portion. The counterweight element is connected to the piezoelectric unit. The fixed portion comprises a bottom that has a first through hole and a second through hole. The first through hole corresponds to the piezoelectric unit and the counterweight element, accommodates a part of the piezoelectric unit and the counterweight element. The second through hole corresponds to the guiding element, accommodates the second end of the guiding element.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: February 11, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Shu-Shan Chen, Pai-Jui Cheng
  • Publication number: 20250044294
    Abstract: The present invention is related to a use of prochlorperazine (PCP), or analog thereof for treating a cancer in a subject by influencing membrane proteins and receptors and inducing alterations in the expressions of the surface marker on cancer cells and their derived extracellular vesicles. The invention method offers a novel approach for the treatment and diagnosis of cancer and metastasis. Specific surface markers serve as a potential candidate for cancer-associated extracellular vesicles (EVs) and have applications in diagnosis, prognosis, and therapeutic targeting.
    Type: Application
    Filed: July 31, 2024
    Publication date: February 6, 2025
    Applicant: National Yang Ming Chiao Tung University
    Inventors: Chi-Ying HUANG, Wei-Ni TSAI, Cayla SOLOMON, Tai-Shan CHENG, Ming-Hsi CHUANG, Ly James LEE, Peter Mu-Hsin CHANG, Yu-Tang HUANG, Thi Tuong Linh NGUYEN, Yi-Ning LO
  • Publication number: 20250037299
    Abstract: A 3D target detection method based on multimodal fusion and a depth attention mechanism includes the following steps: obtaining and preprocessing original point cloud data and original image data; inputting the preprocessed point cloud data and image data into a 3D target detection network based on multimodal fusion and the depth attention mechanism, where the 3D target detection network based on multimodal fusion and the depth attention mechanism includes a generation phase for 3D bounding box proposals and a refinement phase for 3D bounding boxes, and the network outputs parameters and classification confidence of a target bounding box; training the 3D target detection network based on multimodal fusion and the depth attention mechanism; and processing the collected lidar point cloud data and image data by using the trained detection network, and outputting 3D target information, to realize 3D target detection.
    Type: Application
    Filed: October 10, 2024
    Publication date: January 30, 2025
    Inventors: Zhanwen Liu, Yang Wang, Xing Fan, Shan Lin, Juanru Cheng, Yuande Jiang, Chao Li, Bolin Gao, Yi He, Jin Fan, Nan Yang
  • Publication number: 20250040312
    Abstract: A semiconductor device arrangement structure includes a carrier, a first semiconductor device, a second semiconductor device, a first adhesive part, and a second adhesive part. The first semiconductor device and the second semiconductor device are located on the carrier and separated from each other. The first adhesive part and the second adhesive part are separated from each other. The first adhesive part is located between the first semiconductor device and the carrier, and the second adhesive part is located between the second semiconductor device and the carrier. In a top view, the first adhesive part has a first outer contour surrounding the first semiconductor device. The first outer contour has at least one round corner.
    Type: Application
    Filed: July 26, 2024
    Publication date: January 30, 2025
    Inventors: Tai-Ni CHU, Wei-Shan HU, Ching-Tai CHENG
  • Publication number: 20250036011
    Abstract: An optical system includes a fixed assembly, a movable part and a driving assembly. The movable part is configured to be connected to an optical module, and the movable part is movable relative to the fixed assembly. The driving assembly is configured to drive the movable part to move relative to the fixed assembly. The optical system further includes a guiding assembly, and the movable part moves relative to the fixed assembly through the guiding assembly.
    Type: Application
    Filed: July 19, 2024
    Publication date: January 30, 2025
    Inventors: Pai-Jui CHENG, Shu-Shan CHEN, Chuan-Min LEE
  • Patent number: 12205550
    Abstract: The disclosure discloses an image display method, an image display device and a display system. The method includes: according to a image to be displayed, determining a maximum brightness value of pixel points in a panel partition to obtain a backlight brightness value corresponding to a backlight partition; acquiring a light diffusion curve of the backlight of the backlight partition incident on the panel partition corresponding to the backlight partition; calculating a compensation ratio of a target pixel to the light diffusion curve, the compensation ratio is a ratio of the maximum brightness value to an actual brightness value; calculating a pixel compensation value of the target pixel according to the image to be displayed and the compensation ratio; adjusting a pixel value of the target pixel point according to the pixel compensation value.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: January 21, 2025
    Assignees: Analogix (Suzhou) Semiconductor Co., LTD.
    Inventors: Lin Cheng, Qinghong Lai, Shan Wang, Jialian Wu