Abstract: A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.

Abstract: The disclosure provides a daisy-chain serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof. The daisy-chain SPI IC includes a first MISO interface circuit, a second MISO interface circuit, a first data enable (DE) interface circuit, and a second DE interface circuit. When the daisy-chain SPI IC is a target slave circuit selected by a master IC for reading target data, the first DE interface circuit outputs a DE signal to the master IC, and the first MISO interface circuit sends back the target data to the master IC based on the timing of the DE signal. When the daisy-chain SPI IC is not the target slave circuit, the signal received by the second DE interface circuit is transmitted to the first DE interface circuit, and the data received by the second MISO interface circuit is transmitted to the first MISO interface circuit.

Abstract: The invention provides a large touch display integrated (LTDI) circuit and an operation method thereof. The LTDI circuit is suitable as a slave IC of an serial peripheral interface (SPI) architecture. The LTDI circuit includes an open-drain circuit and a reload circuit. An output terminal of the open-drain circuit is configured to be coupled to a correctness wire outside the LTDI circuit. The correctness wire is also coupled to an input terminal of a master IC of the SPI architecture, and a potential of the correctness wire is pulled up by a pull-up resistor. The reload circuit is coupled to an input terminal of the open-drain circuit. The reload circuit is configured to check a correctness of a boot up code from the master IC to generate a correctness check result. The reload circuit returns the correctness check result to the master IC via the open-drain circuit and the correctness wire.

Abstract: The invention provides a large touch display integrated (LTDI) circuit and an operation method thereof. The LTDI circuit is suitable as a slave IC of an serial peripheral interface (SPI) architecture. The LTDI circuit includes an open-drain circuit and a reload circuit. An output terminal of the open-drain circuit is configured to be coupled to a correctness wire outside the LTDI circuit. The correctness wire is also coupled to an input terminal of a master IC of the SPI architecture, and a potential of the correctness wire is pulled up by a pull-up resistor. The reload circuit is coupled to an input terminal of the open-drain circuit. The reload circuit is configured to check a correctness of a boot up code from the master IC to generate a correctness check result. The reload circuit returns the correctness check result to the master IC via the open-drain circuit and the correctness wire.

Abstract: The disclosure provides a daisy-chain serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof. The daisy-chain SPI IC includes a first MISO interface circuit, a second MISO interface circuit, a first data enable (DE) interface circuit, and a second DE interface circuit. When the daisy-chain SPI IC is a target slave circuit selected by a master IC for reading target data, the first DE interface circuit outputs a DE signal to the master IC, and the first MISO interface circuit sends back the target data to the master IC based on the timing of the DE signal. When the daisy-chain SPI IC is not the target slave circuit, the signal received by the second DE interface circuit is transmitted to the first DE interface circuit, and the data received by the second MISO interface circuit is transmitted to the first MISO interface circuit.

Abstract: A serial peripheral interface (SPI) integrated circuit (IC) and an operation method thereof are provided. A SPI architecture includes a master IC and a slave IC. When the SPI IC is a master IC, the SPI IC generates first command information for a slave IC, generates first debugging information corresponding to the first command information, and sends the first command information and the first debugging information to the slave IC through a SPI channel. When the SPI IC is the slave IC, the SPI IC receives second command information and second debugging information sent by the master IC through the SPI channel and checks the second command information by using the second debugging information. When the SPI IC is a target slave circuit selected by the master IC, the SPI IC executes the second command information under a condition that the second command information is checked and is correct.

Abstract: A framer rate converter includes: a receiving circuit for receiving a left-view input image data and a right-view input image data, and outputting a left-view output image data and a right-view output image data, each of the left-view input image data and the right-view input image data comprising a plurality of data segments with information of a plurality of color components of pixels of an interleaved frame, respectively, wherein each of the data segments includes information of a same color component only; and a buffer module comprising: a first frame buffer for storing the left-view output image data; and a second frame buffer for storing the right-view output image data; wherein the first frame buffer outputs the left-view output image data buffered more than once, and the second frame buffer outputs the right-view output image data buffered more than once to generate duplication of each interleaved frame.

Abstract: A frame rate converter includes: a receiving circuit for receiving an input image data and accordingly outputting an output image data, the input image data having a plurality of data segments with information of a plurality of color components of pixels of a frame, respectively, wherein each of the data segments includes information of a same color component only; a frame buffer for storing the output image data; and a first multiplexer for selecting one of the output image data outputted from the receiving circuit and the output image data buffered in the frame buffer as an output of the frame rate converter. The first multiplexer outputs the output image data buffered in the frame buffer at least once after outputting the output image data outputted from the receiving circuit to generate at least one duplication of the frame.

Abstract: An image projection device includes an optical correction unit, a panel and a lens. The optical correction unit is utilized for receiving an image and pre-distorting the image to generate a pre-distorted image according to pre-distortion parameters. The panel is coupled to the optical correction unit, and is utilized for receiving and projecting the pre-distorted image. The lens is positioned in front of the panel, where the pre-distorted image projected from the panel passes through the lens, and the pre-distortion parameters correspond to distortion effects caused by the lens.