Abstract: The various implementations described herein include methods and systems for power-efficient processing of neuromuscular signals. In one aspect, a method includes: (i) obtaining a first set of neuromuscular signals; (ii) after determining, using a low-power detector, that the first set of neuromuscular signals require further processing to confirm that a predetermined in-air hand gesture has been performed: (a) processing the first set of neuromuscular signals using a high-power detector; and (b) in accordance with a determination that the processing indicates that the predetermined in-air hand gesture did occur, registering an occurrence of the predetermined in-air hand gesture; (iii) receiving a second set of neuromuscular signals; and (iv) after determining, using the low-power detector and not using the high-power detector, that a different predetermined in-air hand gesture was performed, performing an action in response to the different predetermined in-air hand gesture.

Abstract: Methods and wearable devices for optimizing power consumption using sensor-based position and use determinations are described here. One example method is performed at a device that includes a first sensor configured to operate with a first power consumption rate and a second sensor configured to operate with a second power consumption rate. The method includes, while a component associated with the second sensor is in an inactive state, receiving first sensor data, and determining whether the first sensor data indicates movement of the device. The method also includes, when movement of the device is indicated, operating the second sensor in an active state. The method further includes, after activating the second sensor, when second sensor data from the second sensor indicates that the device has been placed on a user’s body, continuing to operate the second sensor in the active state.

Abstract: A method of assessing impact of applications executed by a computing device on a memory of the computing device includes: storing, in the memory, (i) a plurality of reference write operation sizes, and (ii) for each reference write operation size, a corresponding reference endurance indicator defining a write endurance; executing, at a processor of the computing device interconnected with the memory, a monitor application simultaneously with a test application; via execution of the monitor application at the processor: generating a usage profile for the test application, the usage profile defining a measured write operation size and a measured write operation rate for write operations initiated by the test application; determining an impact indicator for the test application based on the usage profile, the reference write operation sizes and the reference endurance indicators; and presenting the impact indicator.

Abstract: A computing device includes: a memory storing an audio sequence and a reference attribute associated with playback of the audio sequence; a speaker; a microphone; an audio enclosure supporting the speaker and the microphone; a processor configured to: simultaneously (i) control the speaker to play the audio sequence, and (ii) control the microphone to capture a test recording corresponding to playback of the audio sequence; based on a comparison of the reference attribute to a test attribute associated with the test recording, detect occlusion of the audio enclosure; and in response to detecting occlusion of the audio enclosure, generate a notification message.

Abstract: A method of assessing impact of applications executed by a computing device on a memory of the computing device includes: storing, in the memory, (i) a plurality of reference write operation sizes, and (ii) for each reference write operation size, a corresponding reference endurance indicator defining a write endurance; executing, at a processor of the computing device interconnected with the memory, a monitor application simultaneously with a test application; via execution of the monitor application at the processor: generating a usage profile for the test application, the usage profile defining a measured write operation size and a measured write operation rate for write operations initiated by the test application; determining an impact indicator for the test application based on the usage profile, the reference write operation sizes and the reference endurance indicators; and presenting the impact indicator.

Abstract: An application executed on a device reads a portion of a memory during one of an initialization operation and a regular read operation. The application may trigger a preventative read operation during at least one regular read operation. During the preventative read operation the application selects at least one block and at least one page for the preventative read operation. The application determines a cadence for the preventative read operation. The application obtains an error correction code (ECC) status for the portion of the memory, determines if a number of errors associated with the portion is greater than a predefined ECC threshold and performs a correction, responsive to determining that a number of errors associated with the portion is greater than a predefined ECC threshold.

Abstract: An abnormal connection detection method is used between a power supplier and a power receiver. The power supplier and the power receiver are connected through a cable. The cable includes positive and negative power transmission lines. The abnormal connection detection method includes: providing an output voltage from the power supplier, wherein the output voltage is lower than a predetermined voltage threshold; detecting, according to the output voltage, whether an output current generated by the power supplier is higher than a predetermined current threshold; and when the output current is higher than the predetermined current threshold, determining that an abnormal connection occurs between the power supplier and the power receiver.

Abstract: A signal transmitting and receiving system of a display includes a timing controller and at least one source driver. The timing controller is arranged for transmitting a training signal and a data signal. The source driver is coupled to the timing controller via at least one data channel and a lock channel, and is arranged for receiving the training signal and the data signal via the data channel. The timing controller transmits the training signal or the data signal to the source driver by referring to a voltage level of the lock channel, and the voltage level of the lock channel is allowed to be controlled by both the timing controller and the source driver.

Abstract: Power supplies and power controllers are disclosed. A disclosed power supply has a power controller, a power switch, an auxiliary winding, a first circuit and a second circuit. The power controller is a monolithic integrated circuit with a multi-function pin and a gate pin. A control node of the power switch is coupled to the gate pin. The first circuit is coupled between the multi-function pin and the auxiliary winding and has a diode. The second circuit is coupled between the multi-function pin and a ground line, and has a thermistor.

Abstract: A signal transmitting and receiving system of a display includes a timing controller and at least one source driver. The timing controller is arranged for transmitting a training signal and a data signal. The source driver is coupled to the timing controller via at least one data channel and a lock channel, and is arranged for receiving the training signal and the data signal via the data channel. The timing controller transmits the training signal or the data signal to the source driver by referring to a voltage level of the lock channel, and the voltage level of the lock channel is allowed to be controlled by both the timing controller and the source driver.

Abstract: An abnormal connection detection method is used between a power supplier and a power receiver. The power supplier and the power receiver are connected through a cable. The cable includes positive and negative power transmission lines. The abnormal connection detection method includes: providing an output voltage from the power supplier, wherein the output voltage is lower than a predetermined voltage threshold; detecting, according to the output voltage, whether an output current generated by the power supplier is higher than a predetermined current threshold; and when the output current is higher than the predetermined current threshold, determining that an abnormal connection occurs between the power supplier and the power receiver.

Abstract: A method for confirming correctness of a signal includes: providing a current to flow through a time-dependent impedance circuit, wherein the time-dependent impedance circuit provides at least two resistances at two different time points, the current flowing through the time-dependent impedance circuit to generate a first voltage at a first time point, and the current flowing through the time-dependent impedance circuit to generate a second voltage at a second time point, the first voltage and the second voltage being different from each other. When a predetermined relationship exists between the first voltage and the second voltage, it is confirmed that a signal provided from a node coupled to the time-dependent impedance circuit is correct.

Abstract: An application executed on a device reads a portion of a memory during one of an initialization operation and a regular read operation. The application may trigger a preventative read operation during at least one regular read operation. During the preventative read operation the application selects at least one block and at least one page for the preventative read operation. The application determines a cadence for the preventative read operation. The application obtains an error correction code (ECC) status for the portion of the memory, determines if a number of errors associated with the portion is greater than a predefined ECC threshold and performs a correction, responsive to determining that a number of errors associated with the portion is greater than a predefined ECC threshold.

Abstract: A display device includes a printed circuit board, a timing controller, a display panel, a plurality of source drivers, and a plurality of traces. The timing controller is disposed on the printed circuit board for generating a plenty of differential pairs. The source drivers which are disposed on the display panel for receiving the differential pairs are respectively assigned with an identification number, in which each of the source drivers determines a polarity of the differential pair received according to a corresponding identification number assigned to the source driver. Flexible printed circuit boards are connected to the printed circuit board and the display panel, and each of the flexible printed circuit boards is corresponding to some of the source drivers. The traces carrying the differential pairs are connected to the timing controller and to the source drivers through the flexible printed circuit boards.

Abstract: An adaptive slope-compensation method is applied for a switch-mode power supply. The switch-mode power supply has a power switch, and an inductor coupled to an input power. The power switch controls the inductor storing energy or releasing energy to generate an output voltage. The adaptive slope-compensation method includes detecting an inductor current passing through the inductor and to generate an inductor-current detecting voltage, detecting a duty cycle of the power switch, detecting a voltage variation of the inductor-current detecting voltage when the power switch is turned on, generating a slope-compensation signal according to the voltage variation and the duty cycle, and adjusting the timing of turning the power switch on or off. In this way, even if the operation conditions of the input power and the output voltage change, the system still can quickly response and does not generate sub-harmonic oscillation.

Abstract: Power supplies and power controllers are disclosed. A disclosed power supply has a power controller, a power switch, an auxiliary winding, a first circuit and a second circuit. The power controller is a monolithic integrated circuit with a multi-function pin and a gate pin. A control node of the power switch is coupled to the gate pin. The first circuit is coupled between the multi-function pin and the auxiliary winding and has a diode. The second circuit is coupled between the multi-function pin and a ground line, and has a thermistor.

Abstract: An apparatus for controlling a charging circuit is provided. The apparatus includes a first detector, a second detector, and a controller. The first detector detects a voltage level at a first time and generates a first indication value corresponding to the voltage level at the first time, where the voltage level corresponds to an output voltage of the charging circuit. The second detector detects the voltage level at a second time after the first time and generates a second indication value corresponding to the voltage level at the second time. The controller receives the first and second indication values, and generates a control signal according to the first and second indication values for turning the charging circuit on and off.

Abstract: A detecting device for detecting an operating mode is disclosed. The detecting device includes a pulse generator and a hold-up unit. The pulse generator is disposed for issuing a one-shot pulse signal in response to each of button signals respectively. The hold-up unit is disposed for receiving the button signals to respectively generate delayed button signals by way of clock delay determined by a clock signal. The one-shot pulse signal and the delayed button signals are used to determine an operating mode of a system.

Abstract: An integrated circuit and a related method for determining an operation mode are disclosed. The exemplified integrated circuit includes a controller, a multi-function pin, and a mode determination circuit. The controller controls a power switch and is being set to operate in one of the operation modes including a first operation mode and a second operation mode. The multi-function pin is connected to an external resistor. The mode determination circuit detects a signal from the multi-function pin. The signal represents the resistance of the external resistor. If the resistance is within a first range, the controller is operated in the first operation mode. If the resistance is within a second range, the controller is operated in the second operation mode.

Abstract: A power management device of an SD memory card reader includes a power supply regulator and a controller. The controller controls the power supply regulator to provide a memory card voltage according to an external control signal transmitted from a single control pin. Wherein when the external control signal denotes an enable state, the power supply regulator provides the memory card voltage; when the external control signal denotes a disable state, the power supply regulator stops providing the memory card voltage and discharges the load capacitor; and when the external control signal returns to the enable state from the disable state in a predetermined duration, the power supply regulator changes the memory card voltage.