Abstract: Certain embodiments of the present invention enable comparisons between constrained circuit designs by generating timing graphs for circuit designs, mapping timing constraints to the timing graphs, and comparing the mapped timing constraints from different timing graphs. Typically this comparison is made by identifying corresponding nodes in two or more timing graphs. Specific embodiments are also directed to multiple SDC (Synopsis Design Constraint) constraint specifications for a circuit and multiple constraint sets for different operational modes of a circuit.

Abstract: A method for improved processing efficiency of pipeline architecture with a processor. The processor has a first functional unit; a second functional unit; and a control unit electrically connected to the first and the second functional units for generating a plurality of control signals to control the first and the second functional units. The method includes following steps: (a) executing a first calculation task with the first functional unit or the second functional unit; (b) determining an executing time period of a second calculation task with the control unit according to the functional unit executing the first calculation task, an executing time period of the first calculation task, and whether the second calculation task depends upon a result of the first calculation task; and (c) executing the second calculation task with the first functional unit according to the executing time period of the second calculation task determined in step (b).

Abstract: A method for decoding instructions in an execution package with a processor includes using an assembler to assemble instructions into different execution packages. Each instruction has an identification segment and an instruction segment. The method also includes using the assembler to reorder the instructions by separating identification segments from instruction segments, grouping all identification segments of the execution package together, and grouping all instruction segments of the execution package together. The method uses the processor to decode identification segments of the instructions at the same time, and adds a length of each identification segment together to calculate a total length of the execution package.

Abstract: A method for improved processing efficiency of pipeline architecture with a processor. The processor has a first functional unit; a second functional unit; and a control unit electrically connected to the first and the second functional units for generating a plurality of control signals to control the first and the second functional units. The method includes following steps: (a) executing a first calculation task with the first functional unit or the second functional unit; (b) determining an executing time period of a second calculation task with the control unit according to the functional unit executing the first calculation task, an executing time period of the first calculation task, and whether the second calculation task depends upon a result of the first calculation task; and (c) executing the second calculation task with the first functional unit according to the executing time period of the second calculation task determined in step (b).

Abstract: A method of simulating computation instructions for an instruction set simulator. First, a computation instruction is received by the instruction set simulator. Then, an operator and at least one operand of the computation instruction are stored to a data structure, and the computation instruction is simulated without computing flags. If a flag determination is received for simulation, the operator and the operand are read from the data structure. Then, a flag used in the flag determination is computed according to the operator and the operand, and the flag determination is simulated according to the flag.

Abstract: A method for improving instruction selection efficiency in a DSP/RISC compiler. Concurrently obtaining optimal performance and space, the method includes the following steps: determining a semantic tree for a basic block; finding all matching combinations for the semantic tree with reference to a set of patterns; determining cycle number and instruction length for all combinations; filtering the instruction length greater than a predetermined instruction length and extra ones having the same cycle number and instruction length according to the determined cycle number and instruction length; and choosing one combination with the smallest cycle number from the remaining combinations and outputting the one combination as the desired object code.

Abstract: A decoding method for a multi-length-mode instruction set. The decoding method includes the steps of: rearranging a fixed length instruction into an instruction-partitioned part and a zero-filling part; decoding the rearranged instruction as multiple fields based on the rearranged instruction format requirement; and choosing one field from the multiple fields through a multiplexer as the destination register's content according to the length of the desired instruction part. Therefore, the decoding method can support various lengths of instruction sets using an additional multiplexer with a very small additional memory space.

Abstract: A method for decoding instructions in an execution package with a processor includes using an assembler to assemble instructions into different execution packages. Each instruction has an identification segment and an instruction segment. The method also includes using the assembler to reorder the instructions by separating identification segments from instruction segments, grouping all identification segments of the execution package together, and grouping all instruction segments of the execution package together. The method uses the processor to decode identification segments of the instructions at the same time, and adds a length of each identification segment together to calculate a total length of the execution package.