Abstract: Improved puddle processes and methods are provided herein for retaining a processing liquid on a surface of a semiconductor substrate. More specifically, improved methods are provided herein for retaining a puddle within a center region of a semiconductor substrate while the substrate is stationary, or rotating at relatively low rotational speeds. In the disclosed embodiments, a puddle is retained within a center region of the semiconductor substrate by a thin film, which is deposited within a peripheral edge region of the substrate before a processing liquid is dispensed within the center region of the substrate to form the puddle.

Abstract: In general, disclosed herein are methods for producing a chemoselectively modified biomolecule. The method may include providing a biomolecule, which may include a bioconjugation warhead at a specific site of the biomolecule. Also, the method may include selectively oxidizing the halogen donor compound of the bioconjugation warhead at an electrochemically efficient voltage to generate a halogen radical. Also, the method may include contacting the halogen radical with the bioconjugation warhead at a constant voltage to form an electrophilic warhead. Also, the method may include reacting the electrophilic warhead with a coupling partner comprising a nucleophilic group of the biomolecule to conjugate the electrophilic warhead to the biomolecule.

Abstract: A semiconductor device arrangement structure includes a carrier, semiconductor devices, and an adhesive layer. The semiconductor devices are separately disposed on the carrier, and each of the semiconductor devices includes an electrode. The adhesive layer is disposed between the carrier and the semiconductor devices, and the semiconductor devices are attached to the adhesive layer which is a continuous distributed single-layered structure. The adhesive layer includes unselected regions and a selected region, wherein the unselected regions are covered by the semiconductor devices respectively, and the selected region is not covered by the semiconductor devices. The adhesive layer further includes an indentation disposed on a surface of the selected region, and in a cross-sectional view or a top view, the contour of the indentation is a scaled copy of a contour of and the electrode, and the indentation has a depth less than that of the electrode.

Abstract: Embodiments of a wet etch process and methods are disclosed herein to provide uniform wet etching of material within high aspect ratio features. In the present disclosure, a wet etch process is used to etch material within high aspect ratio features, such as deep trenches and holes, provided on a patterned substrate. Uniform wet etching is provided in the present disclosure by ensuring that wall surfaces of the material being etched (or wall surfaces adjacent to the material being etched) exhibit a neutral surface charge when exposed to the etch solution used to etch the material.

Abstract: A semiconductor device arrangement structure includes a carrier, a first semiconductor device, a second semiconductor device, a first adhesive part, and a second adhesive part. The first semiconductor device and the second semiconductor device are located on the carrier and separated from each other. The first adhesive part and the second adhesive part are separated from each other. The first adhesive part is located between the first semiconductor device and the carrier, and the second adhesive part is located between the second semiconductor device and the carrier. In a top view, the first adhesive part has a first outer contour surrounding the first semiconductor device. The first outer contour has at least one round corner.

Abstract: An embodiment of the present disclosure provides a semiconductor device arrangement. This semiconductor device arrangement includes a carrier, a first semiconductor device, a second semiconductor device, a first adhesive portion, and a second adhesive portion. The first semiconductor device and the second semiconductor device are separately arranged on the carrier. The first adhesive portion and the second adhesive portion are separately arranged on the carrier, the first adhesive portion is located between the first semiconductor device and the carrier, and the second adhesive portion is located between the second semiconductor device and the carrier. In the cross-sectional view, the first adhesive portion includes an inclined sidewall, and the inclined sidewall is adjacent to the carrier and forms an interior angle greater than 90 degrees to the carrier.

Abstract: A pixel structure includes a first light-emitting diode for emitting a first light, wherein the first light-emitting diode has a first semiconductor layer, a first light-emitting surface, and a first electrode under the first semiconductor layer away from the first light-emitting surface; a second light-emitting diode for emitting a second light, wherein the second light-emitting diode has a second semiconductor layer, a second light-emitting surface, and a second electrode under the second semiconductor layer away from the second light-emitting surface; a dielectric layer surrounding and contacting the first semiconductor layer and the second light-emitting diode and exposing the first light-emitting surface, the first electrode, the second light-emitting surface and the second electrode; a common conductive structure having a semiconductor layer and a metal layer; and a light-transmitting conductive layer covering and electrical connecting the first light-emitting diode, the second light-emitting diode and

Abstract: Improved processing systems and methods are provided for wet and dry processing of a semiconductor wafer. Provided is an enclosed chamber for processing a semiconductor wafer within a processing space and a drainage system for directing processing fluids out of the processing space. The enclosed chamber includes a top plate and a bottom plate, which physically confine the processing fluids within a relatively small, enclosed processing space. This forces the processing fluids to flow radially across the wafer surface(s) without the need to rotate the wafer. The drainage system contains a conduit that is downstream from the processing space and configured to retain a portion of a processing fluid dispensed within the processing space. The portion retained within the conduit provides a pressure resistance against the processing fluid(s) dispensed within the processing space to improve wet and dry processing of the wafer surfaces.

Abstract: A wavelength conversion unit arrangement includes a carrier and a wavelength conversion unit. The wavelength conversion unit includes a wavelength conversion layer and a filter layer, and the filter layer attaches the wavelength conversion unit to the carrier. The filter layer has a first surface facing the carrier and a second surface opposite the first surface, and the first surface and the second surface have different textures.

Abstract: An embodiment of the present disclosure provides a semiconductor device arrangement. This arrangement includes a substrate, an adhesive structure, and a first semiconductor device. The substrate includes an upper surface. The adhesive structure is located on the upper surface and includes a first concave region. The first semiconductor device includes a lower surface facing toward the adhesive structure and a conductive bump located under the lower surface and in the first concave region. The conductive bump includes a first portion and a second portion. Wherein the lower surface does not contact the adhesive structure, the first portion contacts the first concave region, and the second portion does not contact the first concave region.

Abstract: Embodiments of a wet etch process and methods are disclosed herein to provide uniform wet etching of material formed within features (e.g., trenches, holes, slits, etc.), and on more planar areas of a patterned substrate, when a critical dimension (CD) of the features is relatively small compared to the more planar areas of the patterned substrate. In the present disclosure, uniform wet etching is provided by ensuring that wall surfaces adjacent to the material being etched exhibit a neutral surface charge when exposed to the etch solution used to etch the material.

Abstract: Embodiments of improved process flows and methods are provided in the present disclosure to control fin height and channel area in a fin field effect transistor (FinFET) having gaps of variable CD. More specifically, the present disclosure provides improved transistor fabrication processes and methods that utilize a wet etch process, instead of a dry etch process, to remove the oxide material deposited within the gaps formed between the fins of a FinFET. By utilizing a wet etch process, the improved transistor fabrication processes and methods described herein provide a means to adjust or individually control the fin height of one or more the fins, thereby providing greater control over the channel area of the FinFET.

Abstract: A semiconductor device includes a semiconductor stack, a protective layer on the semiconductor stack, an electrode on the semiconductor stack and electrically connected to the semiconductor stack, and a conductive bump on the electrode. The thickness of the conductive bump is measured from the topmost point of the conductive bump to the uppermost surface of the protective layer. The ratio of the thickness of the conductive bump to the maximum width of the conductive bump is between 0.1 and 0.4, and the electrode is devoid of gold.

Abstract: A membrane probe card includes probes each having a base electrically connected with a trace of a membrane wiring structure, and a probe tip protruding from the base. The base has a tip placement section and an extension section, which extend from a first side edge to a second side edge of the base in order. The probe tip is made by laser processing and electroplating, located at the tip placement section, and provided with a fixed end portion connected with the base in a way that the width of the tip placement section is greater than the width of the fixed end portion. A distance from a center of the probe tip to the first side edge is less than a distance from the center of the probe tip to the second side edge. As such, requirements of fine pitch and probe height may be achieved.

Abstract: Improved processing systems and methods are provided for wet and dry processing of a semiconductor wafer. Provided is an enclosed chamber for processing a semiconductor wafer within a processing space and a drainage system for directing processing fluids out of the processing space. The enclosed chamber includes a top plate and a bottom plate, which physically confine the processing fluids within a relatively small, enclosed processing space. This forces the processing fluids to flow radially across the wafer surface(s) without the need to rotate the wafer. The drainage system contains a conduit that is downstream from the processing space and configured to retain a portion of a processing fluid dispensed within the processing space. The portion retained within the conduit provides a pressure resistance against the processing fluid(s) dispensed within the processing space to improve wet and dry processing of the wafer surfaces.

Abstract: A probe card and a wafer testing assembly thereof are provided. The wafer testing assembly includes a printed circuit board, a space transformer, a plurality of copper pillars and a plurality of strengthening structure units. The printed circuit board includes a bottom surface and a plurality of first contacts arranged on the bottom surface. The space transformer includes a top surface and a plurality of second contacts. The second contacts are arranged on the top surface and corresponding to the first contacts. The copper pillars are respectively arranged between the first contacts and the second contacts. Two ends of each of the copper pillars are respectively electrically connected to the first contacts and the second contacts. The strengthening structure units are arranged on the bottom surface of the printed circuit board and respectively surrounding the copper pillars.

Abstract: The present disclosure combines chemical mechanical polishing (CMP), wet etch and deposition processes to provide improved processes and methods for planarizing an uneven surface of a material layer deposited over a plurality of structures formed on a substrate. A CMP process is initially used to smooth the uneven surface and provide complete local planarization of the material layer above the plurality of structures. After achieving complete local planarization, a wet etch process is used to etch the material layer until a uniform recess is formed between the plurality of structures and the material layer is provided with a uniform thickness across the substrate. In some embodiments, an additional material layer may be deposited and a second CMP process may be used to planarize the additional material layer to provide the substrate with a globally planarized surface.

Abstract: Embodiments of a wet etch process and method are disclosed to provide uniform etching of material formed within features (such as, e.g., trenches, holes, slits, etc.) having different critical dimension (CD). By combining a non-aqueous organic-based etch solution and an aqueous-based etch solution (either in series or in parallel) within a wet etch process, the disclosed embodiments utilize the opposing effects of CD-dependent etching to provide uniform etching of the material, regardless of CD.

Abstract: Improved puddle processes and methods are provided herein for retaining a processing liquid on a surface of a semiconductor substrate. More specifically, improved methods are provided herein for retaining a puddle within a center region of a semiconductor substrate while the substrate is stationary, or rotating at relatively low rotational speeds. In the disclosed embodiments, a puddle is retained within a center region of the semiconductor substrate by a thin film, which is deposited within a peripheral edge region of the substrate before a processing liquid is dispensed within the center region of the substrate to form the puddle.

Abstract: An apparatus for in-situ etching monitoring in a plasma processing chamber includes a continuous wave broadband light source, an illumination system configured to illuminate an area on a substrate with an incident light beam being directed from the continuous wave broadband light source at normal incidence to the substrate, a collection system configured to collect a reflected light beam being reflected from the illuminated area on the substrate, and to direct the reflected light beam to a first light detector, and a controller. The controller is configured to determine a property of the substrate or structures formed thereupon based on a reference light beam and the reflected light beam, and control an etch process based on the determined property. The reference light beam is generated by the illumination system by splitting a portion of the incident light beam and directed to a second light detector.