Abstract: A multi-processor computer system includes a memory bridge configured in a processor socket on a motherboard. The memory bridge module electrically connects a processor bus and a memory bus that connect to the processor socket. Thus, an adjacent processor is capable of accessing an unused memory by way of the processor bus, the memory bridge and the memory bus.

Abstract: A computer system comprises a main board equipped with a HT device. The HT interface comprises a first connector and a riser card. The first connector is compatible with HT Device-Under-Test (HT-DUT) specifications and electrically connected onto the main board. The riser card, inserted onto the main board, includes a second connector compatible with HT-DUT specifications and a third connector compatible with HT expansion (HTX) specifications. The first connector and the second connector are electrically connected for data transmission. Therefore, the main board equipped with both the HT-DUT connector and the HTX connector achieves smaller on-board space and fewer on-board connection interfaces.

Abstract: A multi-processor computer system includes a memory bridge configured in a processor socket on a motherboard. The memory bridge module electrically connects a processor bus and a memory bus that connect to the processor socket. Thus, an adjacent processor is capable of accessing an unused memory by way of the processor bus, the memory bridge and the memory bus.

Abstract: An indicator pin of an input/output controller is used to identifying whether a processor or a bridge is configured in a processor. When a predetermined voltage level of the indicator pin is confirmed, a base input/output system of the computer system renews a coherent/non-coherent HyperTransport link table. Then an initialization procedure is performed in accordance with the renewed coherent/non-coherent HyperTransport link table.

Abstract: A computer system includes a bridge module plugged in a processor socket of a motherboard with multiple processors. The bridge module electrically connects two buses which have the same transmission protocol and connect to the socket. Thus, two processors or a processor and a chip set would communicate each other by the bridge module and the two buses without installing any processors or additional buses.

Abstract: A multiprocessor system is disclosed, which comprises a plurality of processor unit, such as eight processor units, and a plurality of interconnection bus that may be a dual unidirectional point-to-point bus. Every interconnection bus connects predetermined two of the processor units. Particularly, at least two of the interconnection buses are crossed to each other.

Abstract: A multiprocessor system according to this invention comprises a main board, an expansion board, and at least a connection card. The main board comprises a plurality of first processors, such as four (4) CPUs, and at least a first socket. The expansion board comprises a plurality of second processors, such as four (4) CPUs, and at least a second socket. The plurality of first processors selectively communicates with each other by way of a plurality of first processor buses, which may be dual unidirectional point-to-point buses such as HT buses. The plurality of second processors selectively communicates with each other by way of a plurality of second processor buses, which may be dual unidirectional point-to-point buses such as HT bus. The connection card(s) electronically connect(s) to the first socket(s) and the second socket(s) for providing connection between at least one of the first processor of the main board and at least one of the second processor of the expansion board.