Abstract: A video processing circuit coupled to an external memory and for generating a video stream is provided. The external memory stores a part of a first frame. The video processing circuit includes a memory, a control circuit, an image processing circuit, and a video encoding circuit. The control circuit is used for reading a first image block from the external memory and storing the first image block in the memory, the first image block being a part of the first frame. The image processing circuit is used for reading the first image block from the memory and processing the first image block to generate a second image block which is a part of the second frame different from the first frame. The video encoding circuit is used for reading the first image block from the memory and encoding the first image block to generate a part of the video stream.

Abstract: In some aspects, a memory device is provided. The memory device includes a plurality of memory strings and a peripheral circuit. One of the memory strings includes memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells. The peripheral circuit is coupled to the memory strings and configured to, in a pre-pulse period of a program operation, maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell. After applying the second voltage to the dummy word line, the peripheral circuit is further configured to apply a third voltage to the select line to turn off the select transistor.

Abstract: An onboard antenna, a radio equipment and an electronic device. The onboard antenna includes a dielectric substrate, an antenna and a metal block, wherein the antenna is located on the dielectric substrate, a projection of the metal block on a plane where the dielectric substrate is located is not overlapped with a projection of the antenna on the plane where the dielectric substrate is located, the metal block is located on the dielectric substrate in a polarization direction of the antenna, and a distance between a metal edge of the metal block on a side close to the antenna and the antenna is greater than a coupling threshold. Using this onboard antenna, an influence of surface waves on the pattern can be suppressed to a certain extent by arranging the metal block, and a jitter of the antenna pattern can be reduced.

Abstract: In an example embodiment, a screening question-based online screening mechanism is provided to assess job applicants automatically. More specifically, job-specific questions are automatically generated and asked to applicants to assess the applicants using the answers they provide. Answers to these questions are more recent than facts contained in a user profile and thus are more reliable measures of an appropriateness of an applicant's skills for a particular job.

Abstract: Systems and methods for producing a neural network architecture with improved energy consumption and performance tradeoffs are disclosed, such as would be deployed for use on mobile or other resource-constrained devices. In particular, the present disclosure provides systems and methods for searching a network search space for joint optimization of a size of a layer of a reference neural network model (e.g., the number of filters in a convolutional layer or the number of output units in a dense layer) and of the quantization of values within the layer. By defining the search space to correspond to the architecture of a reference neural network model, examples of the disclosed network architecture search can optimize models of arbitrary complexity. The resulting neural network models are able to be run using relatively fewer computing resources (e.g., less processing power, less memory usage, less power consumption, etc.), all while remaining competitive with or even exceeding the performance (e.g.

Abstract: A cipher accelerator is provided. An encryption and decryption circuit is configured to perform an encryption and decryption operation according to a control signal. The encryption and decryption operation includes a plurality of normal rounds and a plurality of redundant rounds. A controller is configured to provide a control signal to the encryption and decryption circuit according to a first variable value and a second variable value. The encryption and decryption circuit is configured to divide the normal rounds into a first normal section and a second normal section according to the first variable value, and divide the redundant rounds into a first redundant section and a second redundant section according to the second variable value. The encryption and decryption circuit is configured to perform the first normal section, the first redundant section, the second normal section, and the second redundant section sequentially.

Abstract: An addition mask value generator is provided. A first operation circuit is configured to obtain first intermediate data according to first output mask value and fourth output mask value. A second operation circuit is configured to obtain the addition output mask value of a first mask group according to first intermediate data and fourth input mask value. A third operation circuit is configured to obtain second intermediate data according to second output mask value and third output mask value. A fourth operation circuit is configured to obtain the addition output mask value of a second mask group according to second intermediate data and second input mask value. The first and second addition input mask values of first mask group are first and second input mask values. The first and second addition input mask values of second mask group are third input mask value and first intermediate data.

Abstract: A carry-lookahead adder is provided. First XOR gate receives a first mask value and a second mask value to provide a variable. First mask unit performs a first mask operation on first input data with the variable to obtain first masked data. A half adder receives the first masked data and second input data to generate a propagation value and an intermediate generation value. Second mask unit performs a second mask operation on the propagation value with a third mask value to obtain second masked data. A logic circuit provides a generation value according to the propagation value, the intermediate generation value and the second mask value. A carry-lookahead generator provides a carry output and a carry value according to a carry input, the generation value and the propagation value. Second XOR gate receives the second masked data and the carry value to provide a sum output.

Abstract: A carry-lookahead adder is provided. A first mask unit performs first mask operation on first input data with the first mask value to obtain first masked data. A second mask unit performs second mask operation on second input data with the second mask value to obtain second masked data. A first XOR gate receives the first and second mask values to provide a variable value. A half adder receives the first and second masked data to generate a propagation value and an intermediate generation value. A third mask unit performs third mask operation on the propagation value with the third mask value to obtain the third masked data. A carry-lookahead generator provides the carry output and the carry value according to carry input, the generation value, and the propagation value. The second XOR gate receives the third masked data and the carry value to provide the sum output.

Abstract: An attenuation apparatus and a test system. The attenuation apparatus includes a signal transmission channel and at least one radiation loss structure, wherein the signal transmission channel is configured to perform transmission attenuation on the energy of a transmitted signal; the radiation loss structure is arranged in the signal transmission channel; the radiation loss structure has a first operating state and a second operating state; when the radiation loss structure is in the first operating state, the radiation loss structure is configured to perform radiation attenuation on the energy of a signal transmitted by the signal transmission channel; and when the radiation loss structure is in the second operating state, the radiation loss structure is configured to perform transmission attenuation on the energy of the signal transmitted by the signal transmission channel.

Abstract: A method for protecting and managing keys is provided. The method includes the following steps. An OTF cipher transmits a request message to a cryptographic engine to request that the cryptographic engine obtain a wrap key when a key is located in an external memory. The cryptographic engine requests the wrap key from a key store. The key store reads and transmits the wrap key to the cryptographic engine. The OTF cipher requests access to a protection key from the key store, and the key store requests that an external memory controller read the protection key from the external memory. The external memory transmits the protection key to the cryptographic engine. The cryptographic engine generates the key according to the wrap key and the protection key and transmits the key to the OTF cipher. The OTF cipher uses the key to perform an encryption and decryption process.

Abstract: A method for operating a memory is disclosed. The memory includes a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines. A first pass voltage is applied to the first dummy word line and applying a second pass voltage to the second dummy word line. A program voltage is applied to a selected word line, wherein a condition is met: a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.

Abstract: A microstrip antenna, an antenna array, a radar, and a vehicle are provided. The microstrip antenna includes: a dielectric layer, and a metal layer and a ground plane layer disposed at two sides of the dielectric layer, wherein the metal layer includes a first radiation patch and a feeding portion; a length of a long side edge of the first radiation patch is determined based on an operating wavelength of the microstrip antenna, and a length of a short side edge of the first radiation patch is smaller than the length of the long side edge; the feeding portion is coupled between a center position of the long side edge of the first radiation patch and a short side edge, and the feeding portion is configured to transmit a high frequency signal to the first radiation patch or to transmit a space radiation signal received by the first radiation patch.

Abstract: A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level.

Abstract: Provided herein are methods and compositions for inhibiting p97, for the treatment of a cancer in a subject, or a symptom thereof. Upon treatment, the cancer, or a symptom thereof is reduced in the subject. Additionally, methods for measuring sensitivity of a subject to p97 inhibition, methods of assessing a pharmaceutical agent for p97 inhibition activity, and methods of assessing the effect of a pharmaceutical agent for p97 inhibition activity in a subject are provided herein.

Abstract: The present disclosure provides a multifunctional LED lamp, which includes: a main lamp body; one or more LED light-emitting modules connected with the main lamp body; a face recognition module disposed on the main lamp body; an infrared sensing module disposed on the main lamp body; a photosensitive module disposed on the main lamp body; and a control module in communication connection with the face recognition module, the infrared sensing module, and the photosensitive module. The multifunctional LED lamp includes multiple working modes, and the control module controls working states of the face recognition module, the infrared sensing module, and the photosensitive module to switch the working modes. By installing different sensors, the LED lamp of the present disclosure integrates various functions such as lighting, security warning, entertainment, lighting, health, etc., and can realize different working modes by combining different sensors.

Abstract: An LED UV sterilization device, including a lens assembly and a light source assembly; the lens assembly includes a plurality of lenses of different materials suitable for light of different wavelengths; the light source assembly includes a visible light source assembly and an ultraviolet light source assembly. Visible light irradiated by the visible light source assembly and invisible ultraviolet light irradiated by the ultraviolet light source assembly pass through lenses of corresponding materials and form an overlapped light spot, so that an irradiation location of the invisible ultraviolet light is indicated by the visible light. The LED UV sterilization device not only realizes safe disinfection and sterilization, but also visualizes the sterilization process. The sterilization process is safer and more reliable, and the sterilization area is more accurate.

Abstract: Described herein are techniques for using a graph neural network to encode online job postings as embeddings. First, an input graph is defined by processing one or more rules to discover edges that connect nodes in an input graph, where the nodes of the input graph represent job postings or standardized job attributes, and the edges are determined based on analyzing a log of user activity directed to online job postings. Next, a graph neural network (GNN) is trained based on an edge prediction task. Finally, once trained, the GNN is used to derive node embeddings for the nodes (e.g., job postings) of the input graph, and in some instances, new online job postings not represented in the original input graph.