Patents by Inventor Shan Ryan

Shan Ryan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power clamp for high voltage integrated circuits
    Patent number: 8908341
    Abstract: A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: December 9, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Manjunatha Prabhu, Mahadeva Iyer Natarajan, Da-Wei Lai, Shan Ryan
  • Driver-based distributed multi-path ESD scheme
    Patent number: 8786990
    Abstract: A driver-based distributed multi-path ESD scheme is disclosed. Embodiments include providing a plurality of I/O cells, wherein each of the I/O cells includes a first driver having a first source, a first drain, and a first gate; and providing a first signal to turn on the first driver in each of the I/O cells during an ESD event to form a plurality of parallel ESD paths that include turned-on first drivers.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: July 22, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Manjunatha Prabhu, Shan Ryan, Mahadeva Iyer Natarajan
  • DRIVER-BASED DISTRIBUTED MULTI-PATH ESD SCHEME
    Publication number: 20130265677
    Abstract: A driver-based distributed multi-path ESD scheme is disclosed. Embodiments include providing a plurality of I/O cells, wherein each of the I/O cells includes a first driver having a first source, a first drain, and a first gate; and providing a first signal to turn on the first driver in each of the I/O cells during an ESD event to form a plurality of parallel ESD paths that include turned-on first drivers.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Manjunatha Prabhu, Shan Ryan, Mahadeva Iyer Natarajan
  • POWER CLAMP FOR HIGH VOLTAGE INTEGRATED CIRCUITS
    Publication number: 20130265676
    Abstract: A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.
    Type: Application
    Filed: April 4, 2012
    Publication date: October 10, 2013
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Manjunatha Prabhu, Mahadeva Iyer Natarajan, Da-Wei Lai, Shan Ryan