Patents by Inventor Shan Su
Shan Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250138678Abstract: A touch detection method for generating a report includes obtaining a position of a touch point; determining a plurality of reference sensor pads according to the position of the touch point; determining a weight for each of the plurality of reference sensor pads according to the position of the touch point; evaluating a first evaluated peak value of the touch point based on sensing values of the plurality of reference sensor pads and the corresponding weights; and determining whether to generate the report for the touch point according to the first evaluated peak value and a first threshold.Type: ApplicationFiled: June 21, 2024Publication date: May 1, 2025Applicant: NOVATEK Microelectronics Corp.Inventors: Chen-Shan Su, Yun-Hsiang Yeh, Ta-Keng Weng, Chung-Cher Lin
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Publication number: 20230387092Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
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Patent number: 11721678Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: GrantFiled: May 25, 2021Date of Patent: August 8, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
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Patent number: 11527073Abstract: A system and method for providing an interpretable and unified representation for trajectory prediction that includes receiving birds-eye image data associated with travel of at least one agent within a roadway environment. The system and method also include analyzing the birds-eye image data to determine a potential field associated with the roadway environment and analyzing the birds-eye image data to determine a potential field associated with a past trajectory of the at least one agent. The system and method further include predicting a future trajectory of the at least one agent based on analysis of the potential fields.Type: GrantFiled: June 25, 2020Date of Patent: December 13, 2022Assignee: HONDA MOTOR CO., LTD.Inventors: Chiho Choi, Shan Su
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Patent number: 11430750Abstract: A semiconductor device package includes a first substrate, an antenna, a support layer, a dielectric layer and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The antenna element is disposed on the second surface of the first substrate. The support layer is disposed on the first surface of the first substrate and at the periphery of the first surface of the first substrate. The support layer has a first surface facing away from the first substrate. The dielectric layer is disposed on the first surface of the support layer and spaced apart from the first substrate. The dielectric layer is chemically bonded to the support layer. The second substrate is disposed on a first surface of the dielectric layer facing away from the support layer.Type: GrantFiled: May 29, 2019Date of Patent: August 30, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wen Hung Huang, Min Lung Huang, Yuh-Shan Su
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Publication number: 20210280565Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: ApplicationFiled: May 25, 2021Publication date: September 9, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
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Patent number: 11018049Abstract: A manufacturing method of an isolation structure includes the following steps. A semiconductor substrate is provided. A trench is formed in the semiconductor substrate. A first film forming process is performed to form a first dielectric layer conformally on the semiconductor substrate and conformally in the trench. An annealing process is performed to densify the first dielectric layer and convert the first dielectric layer into a second dielectric layer. A thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A second film forming process is performed after the annealing process to form a third dielectric layer on the second dielectric layer and in the trench. The trench is filled with the second dielectric layer and the third dielectric layer.Type: GrantFiled: July 6, 2018Date of Patent: May 25, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Shan Su, Chia-Wei Wu
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Patent number: 11018120Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: GrantFiled: June 6, 2019Date of Patent: May 25, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
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Publication number: 20210150225Abstract: A system and method for providing an interpretable and unified representation for trajectory prediction that includes receiving birds-eye image data associated with travel of at least one agent within a roadway environment. The system and method also include analyzing the birds-eye image data to determine a potential field associated with the roadway environment and analyzing the birds-eye image data to determine a potential field associated with a past trajectory of the at least one agent. The system and method further include predicting a future trajectory of the at least one agent based on analysis of the potential fields.Type: ApplicationFiled: June 25, 2020Publication date: May 20, 2021Inventors: Chiho Choi, Shan Su
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Publication number: 20200388600Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: ApplicationFiled: June 6, 2019Publication date: December 10, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
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Publication number: 20200381375Abstract: A semiconductor device package includes a first substrate, an antenna, a support layer, a dielectric layer and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The antenna element is disposed on the second surface of the first substrate. The support layer is disposed on the first surface of the first substrate and at the periphery of the first surface of the first substrate. The support layer has a first surface facing away from the first substrate. The dielectric layer is disposed on the first surface of the support layer and spaced apart from the first substrate. The dielectric layer is chemically bonded to the support layer. The second substrate is disposed on a first surface of the dielectric layer facing away from the support layer.Type: ApplicationFiled: May 29, 2019Publication date: December 3, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wen Hung HUANG, Min Lung HUANG, Yuh-Shan SU
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Patent number: 10636798Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.Type: GrantFiled: October 21, 2019Date of Patent: April 28, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Shan Su, Chia-Wei Wu, Ting-Pang Chung
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Publication number: 20200051985Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.Type: ApplicationFiled: October 21, 2019Publication date: February 13, 2020Inventors: Yu-Shan Su, Chia-Wei Wu, Ting-Pang Chung
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Patent number: 10490556Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.Type: GrantFiled: July 29, 2018Date of Patent: November 26, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Shan Su, Chia-Wei Wu, Ting-Pang Chung
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Publication number: 20190074210Abstract: A manufacturing method of an isolation structure includes the following steps. A semiconductor substrate is provided. A trench is formed in the semiconductor substrate. A first film forming process is performed to form a first dielectric layer conformally on the semiconductor substrate and conformally in the trench. An annealing process is performed to densify the first dielectric layer and convert the first dielectric layer into a second dielectric layer. A thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A second film forming process is performed after the annealing process to form a third dielectric layer on the second dielectric layer and in the trench. The trench is filled with the second dielectric layer and the third dielectric layer.Type: ApplicationFiled: July 6, 2018Publication date: March 7, 2019Inventors: Yu-Shan Su, Chia-Wei Wu
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Patent number: 10204915Abstract: A method of forming a dynamic random access memory (DRAM) includes the following steps. A substrate includes a memory area and a logic area. A stacked structure is formed on the substrate of the memory area and a gate structure is formed on the substrate of the logic area. A first mask layer is formed on the stacked structure and the gate structure. A densification process is performed to densify the first mask layer. A second mask layer is formed on the first mask layer. A part of the second mask layer and a part of the first mask layer are removed to form a first spacer on sidewalls of the gate structure.Type: GrantFiled: February 12, 2018Date of Patent: February 12, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Shan Su, Chia-Wei Wu
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Patent number: 9348397Abstract: A method of power management is to be implemented by a portable electronic device coupled to a portable power bank. The portable power bank is further coupled to an electrical appliance. In the method, the portable electronic device receives power information from the portable power bank, and controls the portable power bank to operate in one of a first mode, in which electrical power is provided to the electrical appliance, and a second mode, in which electrical power is not provided to the electrical appliance, based on whether or not the portable power bank has sufficient amount of power.Type: GrantFiled: March 27, 2014Date of Patent: May 24, 2016Assignees: NATIONAL TAIWAN NORMAL UNIVERSITY, HEALTHIFE CO., LTD.Inventors: Yu-Shan Su, Han-Chao Chang, Chien-Kai Chung, Min-Wei Hung, Jyun-Yi Lai, Shih-Feng Tseng, Wen-Tse Hsiao, I-Lin Wu
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Patent number: 9043711Abstract: A file managing software program for managing a list of elements in a specific sequence in a first file of a computer program, including the steps of copying the first file to form a second file having an identical list of elements as the first file. The user is then permitted to rearrange the sequence of the elements of the second file independently of the sequence of the first file. A display of both the first and the second file list elements is provided to the user. Further embodiments allow the user to categorize, prioritize, and order according to users specified rules of how the second file element list is organized and displayed to provide a more convenient and flexible presentation of the file contents.Type: GrantFiled: January 31, 2007Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Yen-Fu Chen, Ta-Wei Lin, Chih-Wen Su, Shan Su, Meng Li Wong
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Publication number: 20150033046Abstract: A method of power management is to be implemented by a portable electronic device coupled to a portable power bank. The portable power bank is further coupled to an electrical appliance. In the method, the portable electronic device receives power information from the portable power bank, and controls the portable power bank to operate in one of a first mode, in which electrical power is provided to the electrical appliance, and a second mode, in which electrical power is not provided to the electrical appliance, based on whether or not the portable power bank has sufficient amount of power.Type: ApplicationFiled: March 27, 2014Publication date: January 29, 2015Applicants: Healthife Co., Ltd., National Taiwan Normal UniversityInventors: Yu-Shan SU, Han-Chao CHANG, Chien-Kai CHUNG, Min-Wei HUNG, Jyun-Yi LAI, Shih-Feng TSENG, Wen-Tse HSIAO, I-Lin WU
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Patent number: 7681285Abstract: A detachable handle mounting structure includes a handle, a sleeve fixedly provided at one end of the handle for receiving a tool, a socket, which is fixedly provided at a recessed portion on the periphery of the sleeve and has an accommodation open chamber and a bottom center hole cut through the periphery wall of the sleeve, a plug partially inserted into the bottom center hole of the socket and vertically movable in the bottom center hole of the socket between a locking position where the plug is partially projecting into the inside of the sleeve to lock a tool to the sleeve and an unlocking position where the plug is moved away from the inside of the sleeve to unlock the tool that is inserted into the sleeve, and a rotary knob, which has a coupling member coupled to the plug and is rotatable to move the plug vertically in the bottom center hole of the socket between the locking position and the unlocking position.Type: GrantFiled: September 18, 2006Date of Patent: March 23, 2010Assignee: Natura Innovation Ltd.Inventor: Shan Su Hua