Patents by Inventor Shan Su
Shan Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978373Abstract: A pixel detection device includes a data line, a pixel circuit, and a detection circuit. Pixel circuit is coupled to a system high voltage source, a system low voltage source, and a first reference voltage source. Detection circuit is coupled to data line and pixel circuit, and is configured to receive a driving signal and a detection control signal. Detection circuit forms a first detection loop with the system low voltage source and the data line so as to detect whether the pixel circuit is abnormal according to the driving signal and the detection control signal in a first stage. Detection circuit forms a second detection loop with the first reference voltage source, the system low voltage source, the pixel circuit, and the data line so as to detect whether the pixel circuit is abnormal according to the driving signal and the detection control signal in a second stage.Type: GrantFiled: August 16, 2023Date of Patent: May 7, 2024Assignee: AUO CORPORATIONInventors: Shu-Hao Huang, Sung-Yu Su, Rwei-Shan Chen
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Publication number: 20240138326Abstract: A control method for preparing crop nutrient solution, applied in a regulating device, obtains growth data of crops, and determines a growth state of the crops according to the growth data of the crops. The proportion of the nutrient solution required by the crops is determined according to the growth states of the crops, and the culture solution is adjusted according to the proportion of the nutrient solution. After a preset time period, updated growth state of the crops is determined. When the culture solution does not meet the proportion of the nutrient solution corresponding to the updated growth state, the culture solution is adjusted again until the culture solution meet the proportion of the nutrient solution corresponding to the growth state of the crops.Type: ApplicationFiled: March 28, 2023Publication date: May 2, 2024Inventors: YU-SHAN LIN, CHIEN-HAO SU, KAI-SIANG YOU, YAO-WEN TUNG
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Patent number: 11961891Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.Type: GrantFiled: March 21, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pohan Kung, Ying Hsin Lu, I-Shan Huang
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Patent number: 11949000Abstract: A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer.Type: GrantFiled: July 27, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Shang Hsiao, Ching-Hwanq Su, Pin Chia Su, Ying Hsin Lu, I-Shan Huang
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Publication number: 20240069299Abstract: An optical element driving mechanism includes a movable assembly, a fixed assembly, and a driving assembly. The movable assembly is configured to be connected to an optical element. The movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly in a range of motion. The optical element driving mechanism further includes a positioning assembly configured to position the movable assembly at a predetermined position relative to the fixed assembly when the driving assembly is not operating.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Inventors: Chao-Chang HU, Kuen-Wang TSAI, Liang-Ting HO, Chao-Hsi WANG, Chih-Wei WENG, He-Ling CHANG, Che-Wei CHANG, Sheng-Zong CHEN, Ko-Lun CHAO, Min-Hsiu TSAI, Shu-Shan CHEN, Jungsuck RYOO, Mao-Kuo HSU, Guan-Yu SU
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Publication number: 20230387092Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
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Patent number: 11721678Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: GrantFiled: May 25, 2021Date of Patent: August 8, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
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Patent number: 11527073Abstract: A system and method for providing an interpretable and unified representation for trajectory prediction that includes receiving birds-eye image data associated with travel of at least one agent within a roadway environment. The system and method also include analyzing the birds-eye image data to determine a potential field associated with the roadway environment and analyzing the birds-eye image data to determine a potential field associated with a past trajectory of the at least one agent. The system and method further include predicting a future trajectory of the at least one agent based on analysis of the potential fields.Type: GrantFiled: June 25, 2020Date of Patent: December 13, 2022Assignee: HONDA MOTOR CO., LTD.Inventors: Chiho Choi, Shan Su
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Patent number: 11430750Abstract: A semiconductor device package includes a first substrate, an antenna, a support layer, a dielectric layer and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The antenna element is disposed on the second surface of the first substrate. The support layer is disposed on the first surface of the first substrate and at the periphery of the first surface of the first substrate. The support layer has a first surface facing away from the first substrate. The dielectric layer is disposed on the first surface of the support layer and spaced apart from the first substrate. The dielectric layer is chemically bonded to the support layer. The second substrate is disposed on a first surface of the dielectric layer facing away from the support layer.Type: GrantFiled: May 29, 2019Date of Patent: August 30, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Wen Hung Huang, Min Lung Huang, Yuh-Shan Su
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Publication number: 20210280565Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: ApplicationFiled: May 25, 2021Publication date: September 9, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
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Patent number: 11018120Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: GrantFiled: June 6, 2019Date of Patent: May 25, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
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Patent number: 11018049Abstract: A manufacturing method of an isolation structure includes the following steps. A semiconductor substrate is provided. A trench is formed in the semiconductor substrate. A first film forming process is performed to form a first dielectric layer conformally on the semiconductor substrate and conformally in the trench. An annealing process is performed to densify the first dielectric layer and convert the first dielectric layer into a second dielectric layer. A thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A second film forming process is performed after the annealing process to form a third dielectric layer on the second dielectric layer and in the trench. The trench is filled with the second dielectric layer and the third dielectric layer.Type: GrantFiled: July 6, 2018Date of Patent: May 25, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Shan Su, Chia-Wei Wu
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Publication number: 20210150225Abstract: A system and method for providing an interpretable and unified representation for trajectory prediction that includes receiving birds-eye image data associated with travel of at least one agent within a roadway environment. The system and method also include analyzing the birds-eye image data to determine a potential field associated with the roadway environment and analyzing the birds-eye image data to determine a potential field associated with a past trajectory of the at least one agent. The system and method further include predicting a future trajectory of the at least one agent based on analysis of the potential fields.Type: ApplicationFiled: June 25, 2020Publication date: May 20, 2021Inventors: Chiho Choi, Shan Su
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Publication number: 20200388600Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: ApplicationFiled: June 6, 2019Publication date: December 10, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
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Publication number: 20200381375Abstract: A semiconductor device package includes a first substrate, an antenna, a support layer, a dielectric layer and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The antenna element is disposed on the second surface of the first substrate. The support layer is disposed on the first surface of the first substrate and at the periphery of the first surface of the first substrate. The support layer has a first surface facing away from the first substrate. The dielectric layer is disposed on the first surface of the support layer and spaced apart from the first substrate. The dielectric layer is chemically bonded to the support layer. The second substrate is disposed on a first surface of the dielectric layer facing away from the support layer.Type: ApplicationFiled: May 29, 2019Publication date: December 3, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wen Hung HUANG, Min Lung HUANG, Yuh-Shan SU
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Patent number: 10636798Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.Type: GrantFiled: October 21, 2019Date of Patent: April 28, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Shan Su, Chia-Wei Wu, Ting-Pang Chung
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Publication number: 20200051985Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.Type: ApplicationFiled: October 21, 2019Publication date: February 13, 2020Inventors: Yu-Shan Su, Chia-Wei Wu, Ting-Pang Chung
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Patent number: 10490556Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner, a second liner, and a third liner in the first trench and the second trench; performing a surface treatment process to lower stress of the third liner; and planarizing the third liner, the second liner, and the first liner to form a first isolation structure and a second isolation structure.Type: GrantFiled: July 29, 2018Date of Patent: November 26, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Shan Su, Chia-Wei Wu, Ting-Pang Chung
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Publication number: 20190074210Abstract: A manufacturing method of an isolation structure includes the following steps. A semiconductor substrate is provided. A trench is formed in the semiconductor substrate. A first film forming process is performed to form a first dielectric layer conformally on the semiconductor substrate and conformally in the trench. An annealing process is performed to densify the first dielectric layer and convert the first dielectric layer into a second dielectric layer. A thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A second film forming process is performed after the annealing process to form a third dielectric layer on the second dielectric layer and in the trench. The trench is filled with the second dielectric layer and the third dielectric layer.Type: ApplicationFiled: July 6, 2018Publication date: March 7, 2019Inventors: Yu-Shan Su, Chia-Wei Wu
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Patent number: 10204915Abstract: A method of forming a dynamic random access memory (DRAM) includes the following steps. A substrate includes a memory area and a logic area. A stacked structure is formed on the substrate of the memory area and a gate structure is formed on the substrate of the logic area. A first mask layer is formed on the stacked structure and the gate structure. A densification process is performed to densify the first mask layer. A second mask layer is formed on the first mask layer. A part of the second mask layer and a part of the first mask layer are removed to form a first spacer on sidewalls of the gate structure.Type: GrantFiled: February 12, 2018Date of Patent: February 12, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yu-Shan Su, Chia-Wei Wu