Abstract: An IC structure and methods of forming the same are described. In some embodiments, the structure includes a fin structure disposed over a substrate, the fin structure includes first and second segments and a bottom surface between the first and second segments, and the bottom surface includes a plurality of recesses. The structure further includes a dielectric material disposed between the first and second segments of the fin structure, and the dielectric material is disposed on the bottom surface and in the plurality of recesses. The structure further includes a gate structure disposed over the first segment of the fin structure, and the gate structure covers a top surface and side surfaces of the first segment of the fin structure.

Abstract: Embodiments of the present disclosure disclose a Cupriavidus metallidurans CML2, wherein the Cupriavidus metallidurans CML2 is deposited in the China Center for Type Culture Collection with a depository number CCTCC NO: M20231365, and a 16s rDNA of the Cupriavidus metallidurans CML2 has a nucleotide sequence of SEQ ID No. 1.

Abstract: A neck-mounted power bank is suitable for being hung on a user's neck to supply power to an electronic device. The neck-mounted power bank includes a body, a battery, and a pair of adjustable assemblies. The battery is disposed in the body. The pair of adjustable assemblies are respectively connected to two ends of the body, and define a wearing space with the body. The pair of adjustable assemblies can be rotated relative to the body so as to adjust the size of the wearing space. Each of the pair of adjustable assemblies includes a rotate arm and an angle arm. The rotate arm is rotatably connected to a corresponding end of the body. The angle arm is connected to the rotate arm and has a contact surface. The contact surface is suitable for contacting the user's neck.

Abstract: A one-time activation smoke alarm includes a smoke alarm body and a wall-hanging base. The smoke alarm body includes a case and a sliding sheet. An engaging recessed slot and a supporting protrusion platform are respectively formed on two sides of a bottom of the case. The sliding sheet is slidably disposed on the supporting protrusion platform, and a front end of the sliding sheet has a pressed protrusion portion that extends into the engaging recessed slot. An engaging protrusion platform is formed on the wall-hanging base, and at least one abutting protrusion portion protrudes outward from a periphery of the engaging protrusion platform. The engaging protrusion platform and the engaging recessed slot are capable of being engaged and fixed together such that the abutting protrusion portion abuts the pressed protrusion portion and the smoke alarm body activates a detection function.

Abstract: A smoke alarm having a layered structure includes a case, a smoke detecting unit, and a layering plate. The smoke detecting unit is disposed in the case, and includes a smoke collecting box and a control module electrically connected to the smoke collecting box. The layering plate is disposed in the case. The layering plate defines an upper layer space and a lower layer space in the case, the upper layer space is a smoke guiding space, and the smoke collecting box is accommodated in the upper layer space to facilitate smoke-containing air to flow to the smoke collecting box. The lower layer space is a module mounting space, and the control module is accommodated in the lower layer space to facilitate mounting of a sub-module of the control module that is detachable.

Abstract: A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a fin-shaped structure on a substrate, forming a first trench and a second trench in the fin-shaped structure, forming a first dielectric layer in the first trench and the second trench, removing part of the first dielectric layer, forming a second dielectric layer in the first trench and the second trench to form a first single diffusion break (SDB) structure and a second SDB structure, and then forming a gate structure on the fin-shaped structure, the first SDB structure, and the second SDB structure.

Abstract: A humanized anti-neurotensin receptor 1 (NTSR1) antibody or an antigen-binding fragment thereof. Also, a method for treating, prophylactic treating and/or preventing diseases and/or disorders caused by or related to NTSR1 activity and/or signaling, and a method or kit for detecting NTSR1 in a sample.

Abstract: The present application provides a method for process a substrate. The method includes steps of providing a substrate having a sacrificial layer and an insulative layer, forming a polysilicon hardmask on the insulative layer, etching the insulative and sacrificial layers through multiple openings in the polysilicon hardmask to thus form multiple channels, depositing a metal film and a passivation film on the polysilicon hardmask and in the channels, performing a first removal process to remove portions of the passivation film and the metal film above the polysilicon hardmask, performing a second removal process to remove portions of the polysilicon hardmask exposed through the passivation film and the metal film, and performing a third removal process to remove the polysilicon hardmask and portions of the passivation film and the metal film surrounding the polysilicon is hardmask.

Abstract: An IC structure includes a semiconductor substrate; an isolation structure formed in the semiconductor substrate, thereby defining active regions surrounded by the isolation feature; a first well of a first conductivity type formed in the semiconductor substrate; a neutral region formed in the semiconductor substrate and laterally surrounding the first well; a second well of a second conductivity type formed on the semiconductor substrate and laterally surrounding the neutral region, the second conductivity type being opposite to the first conductivity type; a source disposed on the second well of the semiconductor substrate; a drain disposed on the first well of the semiconductor substrate; and a gate structure interposed between the source and the drain. The gate structure is engaging the first well, the neutral region and the second well of the semiconductor substrate. The source, the drain and the gate structure are configured as a FET.

Abstract: A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.

Abstract: In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.

Abstract: A composition in the form of an oil-in-water emulsion for caring for and/or making up keratin materials, comprises: (i) at least one structuring agent selected from saturated C14-C22 fatty acids; (ii) at least one hydrophilic gelling agent capable of swelling in water to form a microgel in the form of particles with a particle size of 50-400 ?m; and (iii) at least one surfactant. A non-therapeutic method for caring for and/or making up keratin materials, comprises applying said composition to the skin.

Abstract: The present application provides a method for manufacturing a capacitor array. The method includes steps of depositing a sacrificial layer on a bottom electrode; depositing an insulative layer on the sacrificial layer; forming a polysilicon hardmask on the insulative layer; etching the insulative layer and the sacrificial layer exposed through a plurality of openings in the polysilicon hardmask to form channels; depositing a metal film on the polysilicon hardmask and in the channels; depositing a passivation film on the metal film; depositing a conductive material in the channels and in contact with the insulative layer and the sacrificial layer; removing the sacrificial layer; and forming a top electrode on the insulative layer.

Abstract: A humanized anti-neurotensin receptor 1 (NTSR1) antibody or an antigen-binding fragment thereof. Also, a method for treating, prophylactic treating and/or preventing diseases and/or disorders caused by or related to NTSR1 activity and/or signaling, and a method or kit for detecting NTSR1 in a sample.

Abstract: A semiconductor structure includes a first level comprising a metal layer within a first dielectric layer formed on a substrate, a second level formed on the first level, the second level comprising an interconnect within a second dielectric layer and a barrier layer formed around the interconnect, and a metal capping layer disposed at an interface between the metal layer and the interconnect, wherein the metal capping layer comprises tungsten (W) and has a thickness of between 20 ? and 40 ?.

Abstract: A thermoelectric driving wearable system includes a thermoelectric device and an electrical stimulating assembly. The thermoelectric device includes two thermal interface material layers and a thermoelectric converting layer. The two thermal interface material layers are configured for contacting a heat source and a cold source, respectively. The thermoelectric converting layer is located between the two thermal interface material layers and configured for generating an electric energy according to a temperature difference between the heat source and the cold source. The electrical stimulating assembly is electrically connected to the thermoelectric device and configured for being disposed at a skin surface, and the electrical stimulating assembly receives the electric energy and transmits a current to a stimulated region.

Abstract: In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.