Abstract: The present disclosure provides a preparation method of an easy-to-cook whole grain based on microwave-induced cracking, and belongs to the technical field of food processing. In the present disclosure, the preparation method of an easy-to-cook whole grain includes the following steps: subjecting a whole grain to a heat-moisture treatment, and conducting short-time microwave-induced cracking, tempering, and cooling to obtain the easy-to-cook whole grain. The easy-to-cook whole grain obtained by the preparation method of the present disclosure has a complete grain, a slightly-expanded volume, and fine cracks on its surface. Compared with unprocessed whole grains, the easy-to-cook whole grain has a water absorption increased from 1.35 times to 1.9 times an original weight of the unprocessed whole grains during rice steaming.

Abstract: A method of determining defect sensitization includes parsing a netlist of a circuit design to determine a plurality of potential defects and partitioning the circuit design into a plurality of blocks. The method also includes generating a graph representing the circuit design and determining a transitive closure of the graph. The method further includes grouping the plurality of potential defects to produce a plurality of groups of potential defects and selecting a potential defect from each group of the plurality of groups to form a simulation group of potential defects. The method also includes simulating the circuit design by injecting, into the circuit design, every potential defect of the simulation group to produce a set of outputs of the plurality of blocks and determining a defect sensitization for the simulation group of potential defects based on the set of outputs of the plurality of blocks.

Abstract: This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.

Abstract: The present invention discloses a plant fertility-associated protein and its application. The present invention claims a method for obtaining male-sterile plants by reducing or inhibiting the activity and/or content of GmMS1 protein in the target plants. The present invention also claims a method for obtaining male-sterile plants by silencing or suppressing the expression of GmMS1 gene or knocking out the GmMS1 gene in the target plants. The present invention is of great significance to the research of plant fertility and the breeding of sterile plants.

Abstract: A secure boot system, a secure boot method, and a secure boot apparatus, adapted for a boot apparatus to boot a host device, are provided. The boot apparatus includes a storage device and a processor. In the method, the processor reads a boot code and a boot key for booting the host device from the storage device, and executes a cryptographic algorithm on the boot code by using the boot key to obtain a runtime signature. Besides, the processor reads an original signature from a secure area in the storage device and uses the same to verify the runtime signature. If the runtime signature and the original signature are consistent with each other, the processor provides the boot code for the host device to execute a boot operation.

Abstract: A microphone jammer includes a base and a signal generator mounted to the base. The signal generator is configured to generate an ultrasonic signal. The jammer also includes one or more transducers mounted to the base and configured to transmit the ultrasonic signal. The one or more transducers are mounted in a curved layout about the base.

Abstract: A control signal transmission circuit and a control signal receiving circuit for an audio/video interface are provided. The control signal transmission circuit includes an audio/video interface encoder, a signal packaging circuit and a data allocator. The audio/video interface encoder is configured to receive an audio packet and supports a user-defined packet format. The signal packaging circuit is configured to receive a first control signal and package the first control signal into a control data packet according to the user-defined packet format. The data allocator is configured to receive a video data and a second control signal and to mix the second control signal and the video data to generate a mixed data packet. The audio/video interface encoder packages the control data packet, the mixed data packet and the audio packet according to an audio/video transmission protocol to generate an audio/video and control data.

Abstract: This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.

Abstract: A control signal transmission circuit and a control signal receiving circuit for an audio/video interface are provided. The control signal transmission circuit includes an audio/video interface encoder, a signal packaging circuit and a data allocator. The audio/video interface encoder is configured to receive an audio packet and supports a user-defined packet format. The signal packaging circuit is configured to receive a first control signal and package the first control signal into a control data packet according to the user-defined packet format. The data allocator is configured to receive a video data and a second control signal and to mix the second control signal and the video data to generate a mixed data packet. The audio/video interface encoder packages the control data packet, the mixed data packet and the audio packet according to an audio/video transmission protocol to generate an audio/video and control data.

Abstract: In modern VLSI technology, often, stacked arrays of smaller sized MOSFETs are used to achieve the desired width and length of a design MOSFET. In analog defect simulation, each physical transistor can contribute to the circuit's defect universe and this can directly lead to tremendous increase in defect simulation time. Here we propose a method of finding equivalent defects in the context of stacked MOSFET arrays that can lead to significant reduction in defect simulation effort and yet provide accurate defect coverage results.

Abstract: A method and an electronic device for enhancing efficiency of searching for a region of interest in a virtual environment are provided. The virtual environment includes a visible scene and an invisible scene. A picture-in-picture (PIP) is displayed in the visible scene as a directional guidance or distance hint related to the region of interest in the invisible scene, thereby saving time and enhancing efficiency of searching for the region of interest.

Abstract: A secure boot system, a secure boot method, and a secure boot apparatus, adapted for a boot apparatus to boot a host device, are provided. The boot apparatus includes a storage device and a processor. In the method, the processor reads a boot code and a boot key for booting the host device from the storage device, and executes a cryptographic algorithm on the boot code by using the boot key to obtain a runtime signature. Besides, the processor reads an original signature from a secure area in the storage device and uses the same to verify the runtime signature. If the runtime signature and the original signature are consistent with each other, the processor provides the boot code for the host device to execute a boot operation.

Abstract: A method and an electronic device for enhancing efficiency of searching for a region of interest in a virtual environment are provided. The virtual environment includes a visible scene and an invisible scene. A picture-in-picture (PIP) is displayed in the visible scene as a directional guidance or distance hint related to the region of interest in the invisible scene, thereby saving time and enhancing efficiency of searching for the region of interest.

Abstract: A power MOSFET including a first transistor and a second transistor is provided. The first and the second transistors respectively include following elements. A well region is located in a substrate structure. A trench gate is disposed in the well region. First doped regions are disposed in the well region at two sides of the trench gate. A first metal layer is disposed on a first surface of the substrate structure and electrically connected to the first doped regions. A second doped region is disposed in the substrate structure. A second metal layer is disposed on a second surface of the substrate structure opposite to the first surface and electrically connected to the second doped region. The well regions of the first and the second transistors are separated from each other. The first and the second transistors share the second doped region and the second metal layer.

Abstract: A positioning device and a positioning method thereof are provided. The positioning device can cooperate with a first satellite group and a second satellite group, and it comprises a storage, a receiver and a processor. The receiver is configured to receive a first satellite group signal from the first satellite group and a second satellite group signal from the second satellite group. The processor is electrically connected to the storage and the receiver, and configured to calculate a positioning offset value according to one of the first satellite group signal and the second satellite group signal. In addition, the processor is configured to calculate a positioning result according to the second satellite group signal and the positioning offset, and store the positioning result in the storage.

Abstract: In accordance with an exemplary simulation technique, an improved selective application of Newton-Raphson iterations can improve accuracy while ensuring good performance. In this method, selectively applying Newton-Raphson iteration in a simulation of a unit of the integrated circuit design can include determining second order effects to define a linearity value. Newton-Raphson iteration is performed when the linearity value is less than a linearity threshold and convergence of the simulation is not achieved.

Abstract: A global positioning system device and an ionosphere error estimation method thereof are provided. The global positioning system device is connected to a plurality of dual-band base stations, and receives a plurality of ionosphere pierce point coordinates and a plurality of ionosphere errors from the dual-band base stations. The global positioning system device calculates a user ionosphere error by an interpolation method based on the ionosphere pierce point coordinates and the ionosphere errors of the dual-band base stations and a user ionosphere pierce point coordinate of the global positioning system device.

Abstract: In accordance with an exemplary simulation technique, an improved selective application of Newton-Raphson iterations can improve accuracy while ensuring good performance. In this method, selectively applying Newton-Raphson iteration in a simulation of a unit of the integrated circuit design can include determining second order effects to define a linearity value. Newton-Raphson iteration is performed when the linearity value is less than a linearity threshold and convergence of the simulation is not achieved.

Abstract: A global positioning system device and an ionosphere error estimation method thereof are provided. The global positioning system device is connected to a plurality of dual-band base stations, and receives a plurality of ionosphere pierce point coordinates and a plurality of ionosphere errors from the dual-band base stations. The global positioning system device calculates a user ionosphere error by an interpolation method based on the ionosphere pierce point coordinates and the ionosphere errors of the dual-band base stations and a user ionosphere pierce point coordinate of the global positioning system device.

Abstract: A positioning device and a positioning method thereof are provided. The positioning device can cooperate with a first satellite group and a second satellite group, and it comprises a storage, a receiver and a processor. The receiver is configured to receive a first satellite group signal from the first satellite group and a second satellite group signal from the second satellite group. The processor is electrically connected to the storage and the receiver, and configured to calculate a positioning offset value according to one of the first satellite group signal and the second satellite group signal. In addition, the processor is configured to calculate a positioning result according to the second satellite group signal and the positioning offset, and store the positioning result in the storage.