Abstract: A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed.

Abstract: A method and system for testing a semiconductor memory device applies defined test voltages to a semiconductor memory device in a manner that minimizes a time lapse during shifting from one voltage level to another or one voltage range to another. The system includes registers for storing codewords. Each codeword represents a discrete voltage level. The registers have inputs and outputs. Digital-to-analog converters are coupled to the outputs of the registers for converting a codeword into a corresponding analog voltage with a discrete voltage level. A multiplexer derives a test output voltage from the analog voltage, an external voltage, or both. A mode controller controls the multiplexer to derive the test output voltage. The test output voltage is compliant with defined voltage ranges associated with corresponding modes.

Abstract: A memory device with a CAM cell and a read circuit are disclosed for reading a CAM cell using a boosted CAM gate voltage. The CAM read circuit comprises a voltage booster connected between the gate terminal of the CAM cell and a supply voltage, which provides a boosted voltage to the gate terminal of the CAM cell during a CAM read operation. Also disclosed is a method for reading a memory device CAM cell, wherein a boosted voltage is provided to the CAM cell gate.

Abstract: A virtual ground array based flash memory device includes a virtual ground array containing individual memory elements with supporting input/output circuitry. The input/output circuitry contains circuitry for addressing the memory elements as well as transferring data to and from the array, reference circuitry, and comparison circuitry. During sensing, the drains of selected memory elements in the virtual ground array are set to a specific voltage level while the sources of the selected memory elements are used as the sense outputs. The direct current output of one of the selected memory elements is transformed into a voltage and compared to a reference voltage. The direct current from the memory element is then determined by the output of the comparator. The present arrangement and method of sensing from the source side of selected memory elements in the virtual ground array both saves time and conserves power.

Abstract: A flash memory device includes an array of core cell blocks and page buffers with supporting input/output circuitry. The flash memory device, in addition, contains a method for shielding the bitline for a precharging scheme in which the bitline line of each page buffer is charged prior to the sensing/evaluation cycle of a particular memory element in each core cell block. The precharging scheme increases the speed of response in retrieving information from each core cell block because the bitline line is charged to a predetermined voltage prior to accessing the bitline. The bitline shielding method increases the speed of response further by shielding the effects of neighboring bitlines from each other during the evaluation cycle. The shielding method includes charging different bitlines to preset voltages and then maintaining the preset voltages on a set of the bitlines over the evaluation cycle. The preset voltages are maintained on those bitlines not connected with memory elements undergoing evaluation.

Abstract: A virtual ground array based flash memory device includes a virtual ground array containing individual memory elements with supporting input/output circuitry. The threshold voltages of the memory elements gradually increase over operating cycles due to trapping of charge in the nitride or oxide, eventually causing errors due to the increase in threshold voltage. Internal routines are necessary to characterize the change in threshold voltages and subsequently modify the comparison circuit supplying the current used to determine whether the memory elements have attained a specific threshold. The method of automatically adjusting the window of the virtual ground array increases endurance and reliability of the virtual ground array and decreases errors caused by the increased threshold voltage.

Abstract: A virtual ground array based flash memory device includes a virtual ground array containing individual memory elements with supporting input/output circuitry. Variations occur in the threshold voltage of memory elements contained in the virtual ground array caused by excessive usage of the memory elements. Characterization of the variation of threshold voltage as a function of usage as well as the distribution of the various threshold voltages is important for diagnostic purposes. External sources of voltage and means of determination are necessary to characterize the threshold voltages and the I-V characteristics, when the virtual ground array is in a diagnostic mode. In this mode, the drains, sources, and gates of selected memory elements in the virtual ground array may be under independent external control. The current from the source of the selected memory element is determined in response to the externally controlled voltages, thereby creating an I-V curve.

Abstract: A flash memory device includes an array of core cell blocks and page buffers with supporting input/output circuitry. The flash memory device, in addition, contains a mechanism for precharging the bitline line of each page buffer prior to the sensing/evaluation cycle of a particular memory element in each core cell block. The precharging mechanism increases the speed of response in retrieving information from each core cell block because the bitline line is charged to a predetermined voltage prior to accessing the bitline. The precharging mechanism includes a first transistor connected between a power supply and the bitline that is operational during the precharge cycle and causes the bitline to charge to the predetermined voltage. The precharging mechanism also includes a second transistor connected between a latch disposed in the page buffer and ground. The second transistor grounds the latch prior to the start of the evaluation cycle.

Abstract: An electrical rule check program takes simulation output files as input and performs an electrical rule check on the simulation to determine if any electrical design rules have been violated. The program scans a simulation output file to produce a subcircuit name list, an instance name list, and an internal index list for each subcircuit. If the number of circuit nodes is less than a first predetermined value, a window limit is set to equal the number of nodes times the number of data points. If the number of nodes is greater than the first predetermined value and less than a second predetermined value, then the window limit is set to equal some first predetermined fraction of the product of the number of nodes and the number of data points.

Abstract: A two part high voltage check program creates a circuit simulator input file, analyzes the resulting circuit simulator output file for design rule violations, and produces a user report of all violations. The user creates a transistor file which indicates which blocks are to be checked, and optionally specifies individual transistors within the block for checking. The user creates a rule file including rule definitions for the various different types of transistors in the design. The first part generates a print file for input to a circuit simulator. The second part reads the print file, the rule file, and the simulator output file. The second part produces a transistor linked list which is linked to the rule linked list. The second part reads the simulator output file line by line and performs the high voltage electrical rule checks for each transistor for each time step. The second part produces a violation linked lists for each transistor for each violation type.

Abstract: A charge pump circuit having a fast rise time and reduced physical area is disclosed. The charge pump includes a plurality of stages having a non-uniform series of bootstrap capacitors. By using non-uniform capacitors at the various stages, charging rise time is enhanced while at the same time reducing the overall physical size of the charge pump.

Abstract: A high-voltage level shifter includes one or more complementary NMOS/PMOS series intermediate transistor pairs to divide the high-voltage supply range into two or more sub-ranges. The level shifter has a differential structure with complementary NMOS input transistors. Cross-coupled PMOS output transistors provide complementary outputs. The complementary NMOS/PMOS series intermediate transistor pairs separate the NMOS input transistor drains from the PMOS output transistor drains. In order to divide the high voltage range into h subranges, h-1 complementary NMOS/PMOS series intermediate transistor pairs are used each being biased by monotonically increasing fixed intermediate voltages. In a shared-bias embodiment, each complementary NMOS/PMOS series intermediate transistor pair is biased by a single corresponding intermediate voltage.

Abstract: A charge pump circuit having a fast rise time and reduced physical area is disclosed. The charge pump includes a plurality of stages having a non-uniform series of bootstrap capacitors. By using non-uniform capacitors at the various stages, charging rise time is enhanced while at the same time the overall physical size of the charge pump is reduced.

Abstract: Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply.

Abstract: A flash EPROM circuit for providing a tight erase threshold voltage distribution. The circuit includes an array of memory cells having gates, sources and drains. Bit lines are coupled to the drains of a column of cells in the memory array. A plurality of word lines are each coupled to the gates of a row of cells in the memory array. A first voltage source is coupled to the bit lines to converge threshold voltages of erased memory cells. A second voltage source is coupled to the word lines to control the threshold voltages of the erased memory cells.