Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract: A method and apparatus for synchronizing data transfers from a first clock domain to a second clock domain includes sampling data from circuit included in the first clock domain. The clock signal from the first clock domain may then be synchronized to a clock signal from the second clock domain. The sampled data may then be captured using the clock signal from the second clock domain responsive to a detection of an edge of the synchronized first clock signal.

Abstract: An apparatus for synchronizing two clock signals is disclosed. The apparatus may include a selection unit and circuitry. The selection unit may be configured to select a first or second clock signal as an output clock signal. A frequency of the first clock signal may be less than a frequency of the second clock signal. The circuitry may be configured to send a first signal to the selection unit, causing the selection unit to select the first clock signal. The circuitry may also be configured to send a second signal to the selection unit, causing the selection unit to select a subset of clock pulses of the second clock signal as the output clock signal. The subset of clock pulses of the second clock signal may include a clock pulse of the second clock signal corresponding to a transition of the first clock signal.

Abstract: An apparatus for synchronizing a signal from a first clock domain into a second clock domain is disclosed. The apparatus may include circuitry, a synchronization circuit, and a clock gate circuit. The circuitry may de-assert a first enable signal dependent upon a first clock signal. The synchronization circuit may generate a second enable signal synchronized to a second clock signal and may de-assert the second enable signal in response to de-asserting the first enable signal. The clock gate circuit may generate a third clock signal dependent upon the second clock signal, and may disable the third clock signal responsive to de-asserting the second enable signal. The circuitry may further disable the second clock signal in response to determining a predetermined period of time has elapsed since de-asserting the first enable signal.

Abstract: A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit. The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state.

Abstract: An apparatus for synchronizing two clock signals is disclosed. The apparatus may include a selection unit and circuitry. The selection unit may be configured to select a first or second clock signal as an output clock signal. A frequency of the first clock signal may be less than a frequency of the second clock signal. The circuitry may be configured to send a first signal to the selection unit, causing the selection unit to select the first clock signal. The circuitry may also be configured to send a second signal to the selection unit, causing the selection unit to select a subset of clock pulses of the second clock signal as the output clock signal. The subset of clock pulses of the second clock signal may include a clock pulse of the second clock signal corresponding to a transition of the first clock signal.

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

Abstract: A method and apparatus for synchronizing data transfers from a first clock domain to a second clock domain includes sampling data from circuit included in the first clock domain. The clock signal from the first clock domain may then be synchronized to a clock signal from the second clock domain. The sampled data may then be captured using the clock signal from the second clock domain responsive to a detection of an edge of the synchronized first clock signal.

Abstract: An apparatus for synchronizing a signal from a first clock domain into a second clock domain is disclosed. The apparatus may include circuitry, a synchronization circuit, and a clock gate circuit. The circuitry may de-assert a first enable signal dependent upon a first clock signal. The synchronization circuit may generate a second enable signal synchronized to a second clock signal and may de-assert the second enable signal in response to de-asserting the first enable signal. The clock gate circuit may generate a third clock signal dependent upon the second clock signal, and may disable the third clock signal responsive to de-asserting the second enable signal. The circuitry may further disable the second clock signal in response to determining a predetermined period of time has elapsed since de-asserting the first enable signal.

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract: Techniques are disclosed relating to power management within an integrated circuits. In one embodiment an apparatus is disclosed that includes a circuit and a power management unit. The power management unit is configured to provide, based on a programmable setting, an indication of whether an attempted communication to the circuit is permitted to cause the circuit to exit from a power-managed state. In some embodiments, the apparatus includes a fabric configured to transmit the attempted communication to the circuit from a device. In such an embodiment, the circuit is configured to exit the power-managed state in response to receiving the attempted communication. The fabric is configured to determine whether to transmit the attempted communication based on the indication provided by the power management unit.

Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.

Abstract: A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other.

Abstract: A clock divider may provide a lower speed clock to a logic block portion, but during reset, the clock divider may not operate properly, causing the logic block portion to be reset at a clock frequency greater than the frequency for which that logic was designed. However, an extended reset may be employed in which the clock divider is reset normally first before the logic block portion, allowing that logic to be reset according to the divided clock (e.g., rather than a higher speed clock). An asynchronous reset may also be employed in which one or more clock dividers first emerge from reset before being provided with a (synchronized) high speed clock signal, causing the clock dividers to be in phase with each other. This may enable communication between different areas of an IC that might not otherwise be in proper phase with each other.