Patents by Inventor Shane J. Trapp

Shane J. Trapp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240130124
    Abstract: An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.
    Type: Application
    Filed: May 25, 2023
    Publication date: April 18, 2024
    Inventors: Shyam Surthi, Richard J. Hill, Gurtej S. Sandhu, Byeung Chul Kim, Francois H. Fabreguette, Chris M. Carlson, Michael E. Koltonski, Shane J. Trapp
  • Patent number: 11672118
    Abstract: An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shyam Surthi, Richard J. Hill, Gurtej S. Sandhu, Byeung Chul Kim, Francois H. Fabreguette, Chris M. Carlson, Michael E. Koltonski, Shane J. Trapp
  • Publication number: 20220077176
    Abstract: An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.
    Type: Application
    Filed: September 4, 2020
    Publication date: March 10, 2022
    Inventors: Shyam Surthi, Richard J. Hill, Gurtej S. Sandhu, Byeung Chul Kim, Francois H. Fabreguette, Chris M. Carlson, Michael E. Koltonski, Shane J. Trapp
  • Patent number: 10930548
    Abstract: A method of forming an apparatus comprises conformally forming a spacer material over and between structures overlying a base structure. A liner material is conformally formed on the spacer material. The spacer material is selectively etchable relative to the liner material through exposure to at least one etchant. Portions of the liner material and the spacer material overlying upper surfaces of the structures and upper surfaces of the base structure horizontally between the structures are selectively removed to form spacer structures flanking side surfaces of the structures. An apparatus and an electronic system are also described.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shane J. Trapp, Timothy A. Quick, Byeung Chul Kim
  • Publication number: 20200235004
    Abstract: A method of forming an apparatus comprises conformally forming a spacer material over and between structures overlying a base structure. A liner material is conformally formed on the spacer material. The spacer material is selectively etchable relative to the liner material through exposure to at least one etchant. Portions of the liner material and the spacer material overlying upper surfaces of the structures and upper surfaces of the base structure horizontally between the structures are selectively removed to form spacer structures flanking side surfaces of the structures. An apparatus and an electronic system are also described.
    Type: Application
    Filed: January 17, 2019
    Publication date: July 23, 2020
    Inventors: Shane J. Trapp, Timothy A. Quick, Byeung Chul Kim
  • Patent number: 9984977
    Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: May 29, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Ashim Dutta, Mohd Kamran Akhtar, Shane J. Trapp
  • Publication number: 20170263563
    Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 14, 2017
    Applicant: Micron Technology, Inc.
    Inventors: Ashim Dutta, Mohd Kamran Akhtar, Shane J. Trapp
  • Patent number: 9741580
    Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: August 22, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sipani, Anton J. deVilliers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Patent number: 9679852
    Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: June 13, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Ashim Dutta, Mohd Kamran Akhtar, Shane J. Trapp
  • Publication number: 20160005693
    Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.
    Type: Application
    Filed: July 1, 2014
    Publication date: January 7, 2016
    Inventors: Ashim Dutta, Mohd Kamran Akhtar, Shane J. Trapp
  • Publication number: 20150340611
    Abstract: Various embodiments of the present invention are directed to a method for fabricating a memory cell comprising performing a passivation step on a cell structure and cell source lines prior to exhuming a masking layer to prevent oxidation of the cell structure and source lines.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 26, 2015
    Applicant: Sony Corporation
    Inventors: Kamran Akhtar, Ashim Dutta, Alex J. Schrinsky, Shane J. Trapp
  • Publication number: 20150206760
    Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.
    Type: Application
    Filed: March 31, 2015
    Publication date: July 23, 2015
    Inventors: Vishal Sipani, Anton J. deVilliers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Patent number: 8999852
    Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sipani, Anton J. deVillers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Patent number: 8889558
    Abstract: A method of forming a pattern on a substrate includes forming openings in material of a substrate. The openings are widened to join with immediately adjacent of the openings to form spaced pillars comprising the material after the widening. Other embodiments are disclosed.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: November 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Ranjan Khurana, Anton J. deVillers, Kevin J. Torek, Shane J. Trapp, Scott L. Light, James M. Buntin
  • Patent number: 8889559
    Abstract: A method of forming a pattern on a substrate includes forming spaced first material-comprising pillars projecting elevationally outward of first openings formed in second material. Sidewall spacers are formed over sidewalls of the first material-comprising pillars. The sidewall spacers form interstitial spaces laterally outward of the first material-comprising pillars. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall spacers that are over sidewalls of four of the first material-comprising pillars.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: November 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Publication number: 20140162458
    Abstract: A method of forming a pattern on a substrate includes forming openings in material of a substrate. The openings are widened to join with immediately adjacent of the openings to form spaced pillars comprising the material after the widening. Other embodiments are disclosed.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Ranjan Khurana, Anton J. DeVillers, Kevin J. Torek, Shane J. Trapp, Scott L. Light, James M. Buntin
  • Publication number: 20140162459
    Abstract: A method of forming a pattern on a substrate includes forming spaced first material-comprising pillars projecting elevationally outward of first openings formed in second material. Sidewall spacers are formed over sidewalls of the first material-comprising pillars. The sidewall spacers form interstitial spaces laterally outward of the first material-comprising pillars. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall spacers that are over sidewalls of four of the first material-comprising pillars.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Publication number: 20140162457
    Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishal Sipani, Anton J. deVillers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Patent number: 8673787
    Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: March 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Max F. Hineman, Daniel A. Steckert, Jingyi Bai, Shane J. Trapp, Tony Schrock
  • Publication number: 20110250759
    Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.
    Type: Application
    Filed: June 21, 2011
    Publication date: October 13, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gurtej S. Sandhu, Max F. Hineman, Daniel A. Steckert, Jingyi Bai, Shane J. Trapp, Tony Schrock