Patents by Inventor Shane J. Trapp
Shane J. Trapp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130124Abstract: An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.Type: ApplicationFiled: May 25, 2023Publication date: April 18, 2024Inventors: Shyam Surthi, Richard J. Hill, Gurtej S. Sandhu, Byeung Chul Kim, Francois H. Fabreguette, Chris M. Carlson, Michael E. Koltonski, Shane J. Trapp
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Patent number: 11672118Abstract: An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.Type: GrantFiled: September 4, 2020Date of Patent: June 6, 2023Assignee: Micron Technology, Inc.Inventors: Shyam Surthi, Richard J. Hill, Gurtej S. Sandhu, Byeung Chul Kim, Francois H. Fabreguette, Chris M. Carlson, Michael E. Koltonski, Shane J. Trapp
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Publication number: 20220077176Abstract: An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.Type: ApplicationFiled: September 4, 2020Publication date: March 10, 2022Inventors: Shyam Surthi, Richard J. Hill, Gurtej S. Sandhu, Byeung Chul Kim, Francois H. Fabreguette, Chris M. Carlson, Michael E. Koltonski, Shane J. Trapp
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Patent number: 10930548Abstract: A method of forming an apparatus comprises conformally forming a spacer material over and between structures overlying a base structure. A liner material is conformally formed on the spacer material. The spacer material is selectively etchable relative to the liner material through exposure to at least one etchant. Portions of the liner material and the spacer material overlying upper surfaces of the structures and upper surfaces of the base structure horizontally between the structures are selectively removed to form spacer structures flanking side surfaces of the structures. An apparatus and an electronic system are also described.Type: GrantFiled: January 17, 2019Date of Patent: February 23, 2021Assignee: Micron Technology, Inc.Inventors: Shane J. Trapp, Timothy A. Quick, Byeung Chul Kim
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Publication number: 20200235004Abstract: A method of forming an apparatus comprises conformally forming a spacer material over and between structures overlying a base structure. A liner material is conformally formed on the spacer material. The spacer material is selectively etchable relative to the liner material through exposure to at least one etchant. Portions of the liner material and the spacer material overlying upper surfaces of the structures and upper surfaces of the base structure horizontally between the structures are selectively removed to form spacer structures flanking side surfaces of the structures. An apparatus and an electronic system are also described.Type: ApplicationFiled: January 17, 2019Publication date: July 23, 2020Inventors: Shane J. Trapp, Timothy A. Quick, Byeung Chul Kim
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Patent number: 9984977Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.Type: GrantFiled: May 22, 2017Date of Patent: May 29, 2018Assignee: Micron Technology, Inc.Inventors: Ashim Dutta, Mohd Kamran Akhtar, Shane J. Trapp
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Publication number: 20170263563Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.Type: ApplicationFiled: May 22, 2017Publication date: September 14, 2017Applicant: Micron Technology, Inc.Inventors: Ashim Dutta, Mohd Kamran Akhtar, Shane J. Trapp
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Patent number: 9741580Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.Type: GrantFiled: March 31, 2015Date of Patent: August 22, 2017Assignee: Micron Technology, Inc.Inventors: Vishal Sipani, Anton J. deVilliers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
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Patent number: 9679852Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.Type: GrantFiled: July 1, 2014Date of Patent: June 13, 2017Assignee: Micron Technology, Inc.Inventors: Ashim Dutta, Mohd Kamran Akhtar, Shane J. Trapp
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Publication number: 20160005693Abstract: Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps.Type: ApplicationFiled: July 1, 2014Publication date: January 7, 2016Inventors: Ashim Dutta, Mohd Kamran Akhtar, Shane J. Trapp
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Publication number: 20150340611Abstract: Various embodiments of the present invention are directed to a method for fabricating a memory cell comprising performing a passivation step on a cell structure and cell source lines prior to exhuming a masking layer to prevent oxidation of the cell structure and source lines.Type: ApplicationFiled: May 21, 2014Publication date: November 26, 2015Applicant: Sony CorporationInventors: Kamran Akhtar, Ashim Dutta, Alex J. Schrinsky, Shane J. Trapp
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Publication number: 20150206760Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.Type: ApplicationFiled: March 31, 2015Publication date: July 23, 2015Inventors: Vishal Sipani, Anton J. deVilliers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
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Patent number: 8999852Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.Type: GrantFiled: December 12, 2012Date of Patent: April 7, 2015Assignee: Micron Technology, Inc.Inventors: Vishal Sipani, Anton J. deVillers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
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Patent number: 8889558Abstract: A method of forming a pattern on a substrate includes forming openings in material of a substrate. The openings are widened to join with immediately adjacent of the openings to form spaced pillars comprising the material after the widening. Other embodiments are disclosed.Type: GrantFiled: December 12, 2012Date of Patent: November 18, 2014Assignee: Micron Technology, Inc.Inventors: Ranjan Khurana, Anton J. deVillers, Kevin J. Torek, Shane J. Trapp, Scott L. Light, James M. Buntin
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Patent number: 8889559Abstract: A method of forming a pattern on a substrate includes forming spaced first material-comprising pillars projecting elevationally outward of first openings formed in second material. Sidewall spacers are formed over sidewalls of the first material-comprising pillars. The sidewall spacers form interstitial spaces laterally outward of the first material-comprising pillars. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall spacers that are over sidewalls of four of the first material-comprising pillars.Type: GrantFiled: December 12, 2012Date of Patent: November 18, 2014Assignee: Micron Technology, Inc.Inventors: Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
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Publication number: 20140162458Abstract: A method of forming a pattern on a substrate includes forming openings in material of a substrate. The openings are widened to join with immediately adjacent of the openings to form spaced pillars comprising the material after the widening. Other embodiments are disclosed.Type: ApplicationFiled: December 12, 2012Publication date: June 12, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Ranjan Khurana, Anton J. DeVillers, Kevin J. Torek, Shane J. Trapp, Scott L. Light, James M. Buntin
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Publication number: 20140162459Abstract: A method of forming a pattern on a substrate includes forming spaced first material-comprising pillars projecting elevationally outward of first openings formed in second material. Sidewall spacers are formed over sidewalls of the first material-comprising pillars. The sidewall spacers form interstitial spaces laterally outward of the first material-comprising pillars. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall spacers that are over sidewalls of four of the first material-comprising pillars.Type: ApplicationFiled: December 12, 2012Publication date: June 12, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
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Publication number: 20140162457Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.Type: ApplicationFiled: December 12, 2012Publication date: June 12, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Vishal Sipani, Anton J. deVillers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
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Patent number: 8673787Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.Type: GrantFiled: June 21, 2011Date of Patent: March 18, 2014Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Max F. Hineman, Daniel A. Steckert, Jingyi Bai, Shane J. Trapp, Tony Schrock
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Publication number: 20110250759Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.Type: ApplicationFiled: June 21, 2011Publication date: October 13, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Gurtej S. Sandhu, Max F. Hineman, Daniel A. Steckert, Jingyi Bai, Shane J. Trapp, Tony Schrock