Patents by Inventor Shane Norval

Shane Norval has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230136653
    Abstract: A device comprising a liquid crystal cell, wherein the liquid crystal cell comprises LC material contained between opposing surfaces of two components; wherein the opposing surfaces intermesh in at least one or more regions of the LC cell.
    Type: Application
    Filed: March 24, 2021
    Publication date: May 4, 2023
    Inventors: Jan Jongman, Shane Norval
  • Patent number: 11469282
    Abstract: A technique comprising: forming an insulator over a first conductor pattern; patterning the insulator to form an insulator pattern which exposes the first conductor pattern in one or more via regions; forming a second conductor pattern over the insulator pattern, which second conductor pattern contacts said first conductor pattern in said one or more via regions; creating a more even topographic profile in said one or more via regions, with the second conductor pattern exposed outside the one or more via regions; forming a semiconductor (24) over the second conductor pattern for charge carrier transfer between the second conductor pattern and the semiconductor; and depositing a third conductor (26) over the semiconductor, for charge carrier transfer between the third conductor (26) and the semiconductor (24).
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: October 11, 2022
    Assignee: Flexenable Limited
    Inventors: Brian Asplin, Shane Norval, Jan Jongman, Patrick Too
  • Publication number: 20210183907
    Abstract: A device comprising a stack of layers defining one or more electronic elements, wherein the stack comprises at least: one or more semiconductor channels; a dielectric; a first conductor pattern defining one or more coupling conductors, wherein the one or more coupling conductors are capacitively coupled to the one or one or more semiconductor channels via the dielectric; a planarisation layer; a second conductor pattern defining one or more routing conductors, wherein the second conductor pattern is in contact with the first conductor pattern via through holes in at least the planarisation layer, and wherein the semiconductor channel regions are at least partly outside the through hole regions.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 17, 2021
    Inventors: Jan Jongman, Joffrey Dury, Shane Norval
  • Patent number: 10983405
    Abstract: A method, comprising: forming a patterned layer of matrix material and/or one or more patterned layers of colour filter material in situ over a support film; forming in situ over said support film a stack of layers defining electrical circuitry via which each of an array of pixel electrodes is independently addressable; wherein forming said stack of layers comprises forming in situ over said patterned layer of matrix material and/or one or more patterned layers of colour filter material at least: a patterned conductor layer defining an array of source conductors and an array of drain conductors; a layer of semiconductor channel material defining semiconductor channels between the source and drain conductors; and another patterned conductor layer defining an array of gate conductors providing gate electrodes in said channel regions.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: April 20, 2021
    Assignee: FLEXENBLE LIMITED
    Inventor: Shane Norval
  • Publication number: 20200388659
    Abstract: A technique comprising: providing a workpiece including a stack of layers defining an array of transistors including organic semiconductor channels, wherein the stack of layers comprises an upper conductor pattern (8) defining an array of upper conductor elements, each in contact with a respective lower conductor element (6) of a lower conductor pattern in via-hole regions (10); the method comprising: processing the workpiece by forming over the upper conductor pattern a plugging layer that raises the upper surface level of the workpiece in at least the via-hole regions whilst leaving at least a portion of each upper conductor element exposed; and providing an optical medium (36) over the upper conductor pattern without first forming an inorganic moisture barrier layer on the upper surface of the workpiece.
    Type: Application
    Filed: November 12, 2018
    Publication date: December 10, 2020
    Inventors: Charlotte Harrison, Shane Norval
  • Publication number: 20200251544
    Abstract: A technique comprising: forming an insulator over a first conductor pattern; patterning the insulator to form an insulator pattern which exposes the first conductor pattern in one or more via regions; forming a second conductor pattern over the insulator pattern, which second conductor pattern contacts said first conductor pattern in said one or more via regions; creating a more even topographic profile in said one or more via regions, with the second conductor pattern exposed outside the one or more via regions; forming a semiconductor (24) over the second conductor pattern for charge carrier transfer between the second conductor pattern and the semiconductor; and depositing a third conductor (26) over the semiconductor, for charge carrier transfer between the third conductor (26) and the semiconductor (24).
    Type: Application
    Filed: October 1, 2018
    Publication date: August 6, 2020
    Inventors: Brian Asplin, Shane Norval, Jan Jongman, Patrick Too
  • Patent number: 10541258
    Abstract: There is provided a method of patterning a stack of layers defining one or more electronic device elements, comprising: creating a first thickness profile in an uppermost portion of the stack of layers by laser ablation; and etching the stack of layers to translate the first thickness profile into a second thickness profile at a lower level; wherein the etching reduces the thickness of said uppermost portion of the stack and one or more lower layers of the stack under said uppermost portion.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: January 21, 2020
    Assignee: FLEXENABLE LIMITED
    Inventor: Shane Norval
  • Publication number: 20200012131
    Abstract: A method, comprising: forming a patterned layer of matrix material and/or one or more patterned layers of colour filter material in situ over a support film; forming in situ over said support film a stack of layers defining electrical circuitry via which each of an array of pixel electrodes is independently addressable; wherein forming said stack of layers comprises forming in situ over said patterned layer of matrix material and/or one or more patterned layers of colour filter material at least: a patterned conductor layer defining an array of source conductors and an array of drain conductors; a layer of semiconductor channel material defining semiconductor channels between the source and drain conductors; and another patterned conductor layer defining an array of gate conductors providing gate electrodes in said channel regions.
    Type: Application
    Filed: July 2, 2019
    Publication date: January 9, 2020
    Applicant: FLEXENABLE LIMITED
    Inventor: Shane NORVAL
  • Patent number: 9985207
    Abstract: A method of producing an electronic device including the steps of: (i) providing a body including a first, conductive element separated from a first surface of said body by a portion of said body; (ii) removing a selected portion of said body to define a recess in said body extending from said first surface and via which a portion of said first element is exposed; and (iii) putting into said recess a liquid medium carrying a first material; wherein said first material is preferentially deposited on the exposed inner surface of said body defining said recess, and wherein the deposited first material is used to provide a connection between said first element and a second conductive element located within said body or later deposited over said first surface of said body.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: May 29, 2018
    Assignee: FLEXENABLE LIMITED
    Inventors: Carl Hayton, Henning Sirringhaus, Timothy Von Werne, Shane Norval
  • Patent number: 9755010
    Abstract: A pixel driver circuit having only three conductive layers is described. The pixel driver circuit comprises a vertical driver transistor (26) spanning said three conductive layers, wherein a first of said conductive layers (22) on a first side of a middle conductive layer (32) provides a first source-drain connection (52) of said driver transistor, wherein a third of said conductive layers (34) on the opposite side of said middle conductive layer to said first conductive layer provides a gate connection (54) for said vertical driver transistor, and wherein said middle conductive layer provides a second source-drain connection (50) for said vertical driver transistor. The circuit also comprises a lateral switching transistor (30) with source-drain connections (44,46) in one of said three conductive layers.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: September 5, 2017
    Assignee: FlexEnable Limited
    Inventors: Aleksandra Rankov, Charlotte Harrison, Ian Horne, Shane Norval, Jeremy Hills, Burag Yaglioglu
  • Publication number: 20170236850
    Abstract: There is provided a method of patterning a stack of layers defining one or more electronic device elements, comprising: creating a first thickness profile in an uppermost portion of the stack of layers by laser ablation; and etching the stack of layers to translate the first thickness profile into a second thickness profile at a lower level; wherein the etching reduces the thickness of said uppermost portion of the stack and one or more lower layers of the stack under said uppermost portion.
    Type: Application
    Filed: August 18, 2015
    Publication date: August 17, 2017
    Applicant: FLEXENABLE LIMITED
    Inventor: Shane NORVAL
  • Publication number: 20160307987
    Abstract: A pixel driver circuit having only three conductive layers is described. The pixel driver circuit comprises a vertical driver transistor (26) spanning said three conductive layers, wherein a first of said conductive layers (22) on a first side of a middle conductive layer (32) provides a first source-drain connection (52) of said driver transistor, wherein a third of said conductive layers (34) on the opposite side of said middle conductive layer to said first conductive layer provides a gate connection (54) for said vertical driver transistor, and wherein said middle conductive layer provides a second source-drain connection (50) for said vertical driver transistor. The circuit also comprises a lateral switching transistor (30) with source-drain connections (44,46) in one of said three conductive layers.
    Type: Application
    Filed: December 3, 2014
    Publication date: October 20, 2016
    Inventors: Aleksandra Rankov, Charlotte Harrison, Ian Horne, Shane Norval, Jeremy Hills, Burag Yaglioglu
  • Publication number: 20140057433
    Abstract: A technique comprising: forming laterally-extending switching circuitry of a device for controlling an overlying laterally-extending array of pixel conductors of said device; forming an electrically conductive laterally-extending patterned screen over said switching circuitry via a first insulating region, said patterned screen defining holes for receiving conductive interlayer connects between said switching circuitry and said array of pixel conductors; and thereafter: forming a second insulating region over said patterned screen, forming said array of pixel conductors over said patterned screen via said second insulating region for capacitative coupling with said patterned screen, forming through holes through at least said first and second insulating regions at the locations of said holes defined in said patterned screen, and forming said interlayer connects in said through holes; and wherein said patterned screen is configured such that the area of overlap between the array of pixel conductors and underly
    Type: Application
    Filed: April 11, 2012
    Publication date: February 27, 2014
    Applicant: PLASTIC LOGIC LIMITED
    Inventors: Paul Cain, Shane Norval, Boon Hean Pui
  • Publication number: 20130143416
    Abstract: A technique comprising: using a laser beam to ablate a target surface (2) via projection lens (12) as part of a process of defining one or more elements of one or more electronic devices, wherein the ablating is performed whilst extracting material ablated from the target surface via an extraction device inlet (6) having at least a portion at a level between said target surface (2) and said projection lens (12) and at the level of a plume of ablated material above said target surface.
    Type: Application
    Filed: June 3, 2011
    Publication date: June 6, 2013
    Applicant: PLASTIC LOGIC LIMITED
    Inventor: Shane Norval
  • Publication number: 20090232969
    Abstract: A method of producing an electronic device including the steps of: (i) providing a body including a first, conductive element separated from a first surface of said body by a portion of said body; (ii) removing a selected portion of said body to define a recess in said body extending from said first surface and via which a portion of said first element is exposed; and (iii) putting into said recess a liquid medium carrying a first material; wherein said first material is preferentially deposited on the exposed inner surface of said body defining said recess, and wherein the deposited first material is used to provide a connection between said first element and a second conductive element located within said body or later deposited over said first surface of said body.
    Type: Application
    Filed: December 6, 2005
    Publication date: September 17, 2009
    Applicant: Plastic Logic Limited
    Inventors: Carl Hayton, Henning Sirringhaus, Timothy Von Werne, Shane Norval