Patents by Inventor Shane P. Leiphart
Shane P. Leiphart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7456452Abstract: Light sensors in an imager having sloped features including, but not limited to, hemispherical, v-shaped, or other sloped shapes. Light sensors having such a sloped feature can redirect incident light that is not absorbed by one portion of the photosensor to another portion of the photosensor for absorption there.Type: GrantFiled: December 15, 2005Date of Patent: November 25, 2008Assignee: Micron Technology, Inc.Inventors: David Wells, Shane P. Leiphart
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Patent number: 7163893Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.Type: GrantFiled: November 12, 2004Date of Patent: January 16, 2007Assignee: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Patent number: 6833623Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.Type: GrantFiled: August 11, 1999Date of Patent: December 21, 2004Assignee: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Patent number: 6828233Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.Type: GrantFiled: April 11, 2002Date of Patent: December 7, 2004Assignee: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Patent number: 6800180Abstract: An improved apparatus and method for manufacturing semiconductor devices, and, in particular, for depositing material at the bottom of a contact hole, comprises sputtering a material onto a semiconductor substrate; applying a first bias voltage to the substrate, simultaneously removing the material surrounding the contact hole to form a facet at the top of the recess; and applying a second bias voltage to the substrate, simultaneously sputter-depositing the first material onto the bottom of the recess. A further embodiment of the invention utilizes an electrically isolated collimator for the sputtering apparatus. Another embodiment of the invention resputters a first material onto sidewalls of a contact hole during physical vapor deposition.Type: GrantFiled: January 12, 1999Date of Patent: October 5, 2004Assignee: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Patent number: 6660136Abstract: The invention includes methods of forming a non-volatile resistance variable device and methods of forming a metal layer comprising silver and tungsten. A method of forming a non-volatile resistance variable device includes forming a chalcogenide material over a semiconductor substrate. First and second electrodes are formed operably proximate the chalcogenide material. At least one of the first and second electrodes includes a metal layer having silver and tungsten. The metal layer is formed by providing the substrate within a sputter deposition chamber. One or more target(s) is/are provided within the chamber which include(s) at least tungsten and silver. The one or more target(s) is/are sputtered using a sputtering gas comprising at least one of Xe, Kr and Rn under conditions effective to deposit the metal layer onto the substrate. The metal layer can be fabricated independent of fabrication of a non-volatile resistance variable device.Type: GrantFiled: March 27, 2002Date of Patent: December 9, 2003Assignee: Micron Technology, Inc.Inventors: Jiutao Li, Shane P. Leiphart
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Publication number: 20030183507Abstract: The invention includes methods of forming a non-volatile resistance variable device and methods of forming a metal layer comprising silver and tungsten. A method of forming a non-volatile resistance variable device includes forming a chalcogenide material over a semiconductor substrate. First and second electrodes are formed operably proximate the chalcogenide material. At least one of the first and second electrodes includes a metal layer having silver and tungsten. The metal layer is formed by providing the substrate within a sputter deposition chamber. One or more target(s) is/are provided within the chamber which include(s) at least tungsten and silver. The one or more target(s) is/are sputtered using a sputtering gas comprising at least one of Xe, Kr and Rn under conditions effective to deposit the metal layer onto the substrate. The metal layer can be fabricated independent of fabrication of a non-volatile resistance variable device.Type: ApplicationFiled: March 27, 2002Publication date: October 2, 2003Applicant: Micron Technology, Inc.Inventors: Jiutao Li, Shane P. Leiphart
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Publication number: 20020109235Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.Type: ApplicationFiled: April 11, 2002Publication date: August 15, 2002Applicant: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Publication number: 20020025372Abstract: The invention includes methods of forming aluminum containing lines having titanium nitride containing layers thereon, and preferably by physical vapor deposition. In one aspect, a first layer including at least one of elemental aluminum or an aluminum alloy is formed over a substrate. A second layer including an alloy of titanium and the aluminum from the first layer is formed. The alloy has a higher melting point than that of the first layer. A third layer including titanium nitride is formed over the second layer. The first, second and third layers are formed into a conductive line. In one aspect, a method of forming an aluminum containing line having a titanium nitride containing layer thereon includes physical vapor depositing a first layer having at least one of elemental aluminum or an aluminum alloy over a substrate.Type: ApplicationFiled: February 16, 2001Publication date: February 28, 2002Inventor: Shane P. Leiphart
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Patent number: 6346177Abstract: A method of in-situ cleaning and deposition of device structures in a high density plasma environment. A device structure is located in a reaction chamber containing a sputter target. A high density plasma containing ionized gas particles is generated. The ionized gas particles are accelerated toward the device structure during a cleaning phase. The cleaning phase may be divided into a first cleaning phase during which no power is applied to the sputter target and a second cleaning phase during which power is supplied to the sputter target at a level sufficient to remove at least a portion of by-products deposited on the sputter target during the first cleaning phase.Type: GrantFiled: January 12, 2001Date of Patent: February 12, 2002Assignee: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Publication number: 20020008322Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.Type: ApplicationFiled: August 11, 1999Publication date: January 24, 2002Inventor: SHANE P. LEIPHART
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Patent number: 6323124Abstract: An improved apparatus and method for manufacturing semiconductor devices, and, in particular, for depositing material at the bottom of a contact hole, comprises sputtering a material onto a semiconductor substrate; applying a first bias voltage to the substrate, simultaneously removing the material surrounding the contact hole to form a facet at the top of the recess; and applying a second bias voltage to the substrate, simultaneously sputter-depositing the first material onto the bottom of the recess. A further embodiment of the invention utilizes an electrically isolated collimator for the sputtering apparatus. Another embodiment of the invention resputters a first material onto sidewalls of a contact hole during physical vapor deposition.Type: GrantFiled: January 12, 1999Date of Patent: November 27, 2001Assignee: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Patent number: 6258718Abstract: A process of forming a layer of conductive material over a layer of insulating material is provided. A wafer is positioned on a wafer platform such that it is thermally and electrically coupled to the wafer platform. A clamping ring engages the peripheral edge of the wafer such that the wafer is held against the top surface of the wafer platform. The clamping ring is electrically coupled to the wafer pedestal. The wafer is exposed to a plasma comprising conductive material and an initial layer of conductive material is formed over the insulating layer until the top surface of the wafer is electrically coupled to the clamping ring. The wafer pedestal is then electrically biased and additional conductive material is formed. Once the initial layer of conductive material is electrically coupled to the clamping ring, the potential difference between the top and bottom surface of the wafer is zero such that arcing through the wafer is reduced.Type: GrantFiled: January 13, 2000Date of Patent: July 10, 2001Assignee: Micron Technology, Inc.Inventors: Shane P. Leiphart, Randle D. Burton
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Publication number: 20010001190Abstract: A method of in-situ cleaning and deposition of device structures in a high density plasma environment. A device structure is located in a reaction chamber containing a sputter target. An ion containing gas located in the reaction chamber is exposed to an RF voltage to generate a high density plasma containing ionized gas particles. The ionized gas particles are accelerated toward the device structure during a cleaning phase. By-products produced during the cleaning phase are either evacuated from the reaction chamber or platted to the chamber walls. Ionized gas particles are then accelerated toward the sputter target during a deposition phase so that a layer of the sputter target material is deposited on at least a portion of the device structure.Type: ApplicationFiled: January 12, 2001Publication date: May 17, 2001Applicant: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Patent number: 6224942Abstract: The invention includes methods of forming aluminum containing lines having titanium nitride containing layers thereon, and preferably by physical vapor deposition. In one aspect, a first layer including at least one of elemental aluminum or an aluminum alloy is formed over a substrate. A second layer including an alloy of titanium and the aluminum from the first layer is formed. The alloy has a higher melting point than that of the first layer. A third layer including titanium nitride is formed over the second layer. The first, second and third layers are formed into a conductive line. In one aspect, a method of forming an aluminum containing line having a titanium nitride containing layer thereon includes physical vapor depositing a first layer having at least one of elemental aluminum or an aluminum alloy over a substrate.Type: GrantFiled: August 19, 1999Date of Patent: May 1, 2001Assignee: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Patent number: 6187151Abstract: A method of in-situ cleaning and deposition of device structures in a high density plasma environment. A device structure is located in a reaction chamber containing a sputter target. An ion containing gas located in the reaction chamber is exposed to an RF voltage to generate a high density plasma containing ionized gas particles. The ionized gas particles are accelerated toward the device structure during a cleaning phase. By-products produced during the cleaning phase are either evacuated from the reaction chamber or platted to the chamber walls. Ionized gas particles are then accelerated toward the sputter target during a deposition phase so that a layer of the sputter target material is deposited on at least a portion of the device structure.Type: GrantFiled: January 2, 1997Date of Patent: February 13, 2001Assignee: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Patent number: 6171459Abstract: An improved apparatus and method for manufacturing semiconductor devices, and, in particular, for depositing material at the bottom of a contact hole, comprises sputtering a material onto a semiconductor substrate; applying a first bias voltage to the substrate, simultaneously removing the material surrounding the contact hole to form a facet at the top of the recess; and applying a second bias voltage to the substrate, simultaneously sputter-depositing the first material onto the bottom of the recess. A further embodiment of the invention utilizes an electrically isolated collimator for the sputtering apparatus. Another embodiment of the invention resputters a first material onto sidewalls of a contact hole during physical vapor deposition.Type: GrantFiled: January 12, 1999Date of Patent: January 9, 2001Assignee: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Patent number: 6090246Abstract: Methods and apparatus for detecting neutral gas molecules reflected from a target material during a sputter deposition process are disclosed to improve the uniformity of sputter depositing a metal film on a substrate. In a preferred embodiment, an electrically grounded collimator is positioned between the target material and a substrate in a sputtering chamber to restrict a plasma in the chamber to an area away from the substrate. The plasma is prevented from inducing a negative voltage on the substrate, and voltage measurements in the chamber can be taken in the proximate vicinity of the substrate without electrical influence from the charged plasma. It has been discovered that when these voltage measurements show a measurable increase in voltage in the proximate vicinity of the substrate, high energy reflected neutrals are impacting upon the substrate.Type: GrantFiled: January 20, 1998Date of Patent: July 18, 2000Assignee: Micron Technology, Inc.Inventor: Shane P. Leiphart
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Patent number: 6057235Abstract: A process of forming a layer of conductive material over a layer of insulating material is provided. A wafer is positioned on a wafer platform such that it is thermally and electrically coupled to the wafer platform. A clamping ring engages the peripheral edge of the wafer such that the wafer is held against the top surface of the wafer platform. The clamping ring is electrically coupled to the wafer pedestal. The wafer is exposed to a plasma comprising conductive material and an initial layer of conductive material is formed over the insulating layer until the top surface of the wafer is electrically coupled to the clamping ring. The wafer pedestal is then electrically biased and additional conductive material is formed. Once the initial layer of conductive material is electrically coupled to the clamping ring, the potential difference between the top and bottom surface of the wafer is zero such that arcing through the wafer is reduced.Type: GrantFiled: September 15, 1997Date of Patent: May 2, 2000Assignee: Micron Technology, Inc.Inventors: Shane P. Leiphart, Randle D. Burton
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Patent number: 5997699Abstract: A semiconductor substrate having thereon a surface including features to be filled is placed in a vacuum chamber having a high density plasma source and a target of material to be deposited. A vacuum is drawn, and a plasma is struck in a gas by means of the high density plasma source. The substrate is then biased to cause ions from the plasma to bombard the substrate with energies sufficient to facet top corners of features on the surface of the substrate. After a desired amount of faceting has occurred, the target is biased to cause ions from the plasma to sputter the target, resulting in a plasma comprised of target material and the gas. The substrate is then biased sufficiently to provide a near perpendicular flow of ions of target material to the substrate, but at sufficiently low energy to deposit a film of the material to be deposited. The substrate bias may be held sufficiently high to prevent or reduce buildup on the facets.Type: GrantFiled: April 8, 1996Date of Patent: December 7, 1999Assignee: Micron Technology Inc.Inventor: Shane P. Leiphart