Patents by Inventor Shane Patrick Geary

Shane Patrick Geary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563084
    Abstract: A bipolar junction transistor is provided with an emitter structure that is positioned above the upper surface of the base region. The thickness of the emitter and the interfacial oxide thickness between the emitter and the base is configured to optimize a gain for a given type of transistor. A method of fabricating PNP and NPN transistors on the same substrate using a complementary bipolar fabrication process is provided. The method enables the emitter structure for the NPN transistor to be defined separately to that of the PNP transistor. This is achieved by epitaxially growing the emitter layer for the PNP transistor and growing the emitter layer for the NPN transistor in a thermal furnace.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: January 24, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Edward John Coyne, Alan Brannick, Shane Tooher, Breandán Pol Og Ó hAnnaidh, Catriona Marie O'Sullivan, Shane Patrick Geary
  • Patent number: 11404540
    Abstract: A bipolar junction transistor is provided with a multilayer collector structure. The layers of the collector are individually grown in separate epitaxial growth stages. For a PNP transistor, each layer, after it is grown, is doped with a p-type dopant in a dedicated implant stage. By providing separate epitaxial growth stages and separate dopant implant stages for each layer of the collector, the dopant concentration profile in the collector region can be better controlled to optimize the speed and breakdown voltage of a bipolar junction transistor.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: August 2, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Edward John Coyne, Alan Brannick, Shane Tooher, Breandán Pol Og ÓhAnnaidh, Catriona Marie O'Sullivan, Shane Patrick Geary
  • Patent number: 11355585
    Abstract: A charge control structure is provided for a bipolar junction transistor to control the charge distribution in the depletion region extending into the bulk collector region when the collector-base junction is reverse-biased. The charge control structure comprises a lateral field plate above the upper surface of the collector and dielectrically isolated from the upper surface of the collector and a vertical field plate which is at a side of the collector and is dielectrically isolated from the side of the collector. The charge in the depletion region extending into the collector is coupled to the base as well as the field-plates in the charge-control structure, instead of only being coupled to the base of the bipolar junction transistor. In this way, a bipolar junction transistor is provided where the dependence of collector current on the collector-base voltage, also known as Early effect, can be reduced.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: June 7, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Edward John Coyne, Alan Brannick, Shane Tooher, Breandán Pol Og Ó hAnnaidh, Catriona Marie O'Sullivan, Shane Patrick Geary
  • Publication number: 20210098575
    Abstract: A charge control structure is provided for a bipolar junction transistor to control the charge distribution in the depletion region extending into the bulk collector region when the collector-base junction is reverse-biased. The charge control structure comprises a lateral field plate above the upper surface of the collector and dielectrically isolated from the upper surface of the collector and a vertical field plate which is at a side of the collector and is dielectrically isolated from the side of the collector. The charge in the depletion region extending into the collector is coupled to the base as well as the field-plates in the charge-control structure, instead of only being coupled to the base of the bipolar junction transistor. In this way, a bipolar junction transistor is provided where the dependence of collector current on the collector-base voltage, also known as Early effect, can be reduced.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Edward John Coyne, Alan Brannick, Shane Tooher, Breandán Pol Og Ó hAnnaidh, Catriona Marie O'Sullivan, Shane Patrick Geary
  • Publication number: 20210098576
    Abstract: A bipolar junction transistor is provided with a multilayer collector structure. The layers of the collector are individually grown in separate epitaxial growth stages. For a PNP transistor, each layer, after it is grown, is doped with a p-type dopant in a dedicated implant stage. By providing separate epitaxial growth stages and separate dopant implant stages for each layer of the collector, the dopant concentration profile in the collector region can be better controlled to optimize the speed and breakdown voltage of a bipolar junction transistor.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Edward John Coyne, Alan Brannick, Shane Tooher, Breandán Pol Og Ó hAnnaidh, Catriona Marie O'Sullivan, Shane Patrick Geary
  • Publication number: 20210098574
    Abstract: A bipolar junction transistor is provided with an emitter structure that is positioned above the upper surface of the base region. The thickness of the emitter and the interfacial oxide thickness between the emitter and the base is configured to optimize a gain for a given type of transistor. A method of fabricating PNP and NPN transistors on the same substrate using a complementary bipolar fabrication process is provided. The method enables the emitter structure for the NPN transistor to be defined separately to that of the PNP transistor. This is achieved by epitaxially growing the emitter layer for the PNP transistor and growing the emitter layer for the NPN transistor in a thermal furnace.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Edward John Coyne, Alan Brannick, Shane Tooher, Breandán Pol Og Ó hAnnaidh, Catriona Marie O'Sullivan, Shane Patrick Geary
  • Publication number: 20180061569
    Abstract: The disclosure relates to the manufacture of inductive components, in particular transformers, using a combination of microfabrication techniques and discrete component placement. By using a prefabricated core, the core may be made much thicker than one that is deposited using microfabrication techniques. As such, saturation occurs later and the efficiency of the transformer is improved. This is done at a much lower cost than the cost of producing a thicker core by depositing multiple layers using microfabrication techniques.
    Type: Application
    Filed: August 26, 2016
    Publication date: March 1, 2018
    Applicant: Analog Devices Global
    Inventors: Jan Kubík, Bernard Patrick Stenson, Shane Patrick Geary, Michael Noel Morrissey
  • Patent number: 9484136
    Abstract: A magnetic core is provided for an integrated circuit, the magnetic core comprising: a plurality of layers of magnetically functional material; a plurality of layers of a first insulating material; and at least one layer of an secondary insulating material; wherein layers of the first insulating material are interposed between layers of the magnetically functional material to form subsections of the magnetic core, and the at least one layer of second insulating material is interposed between adjacent subsections.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: November 1, 2016
    Assignee: Analog Devices Global
    Inventors: Michael Noel Morrissey, Jan Kubik, Shane Patrick Geary, Patrick Martin McGuinness, Catriona Marie O'Sullivan
  • Publication number: 20140062646
    Abstract: A magnetic core is provided for an integrated circuit, the magnetic core comprising: a plurality of layers of magnetically functional material; a plurality of layers of a first insulating material; and at least one layer of an secondary insulating material; wherein layers of the first insulating material are interposed between layers of the magnetically functional material to form subsections of the magnetic core, and the at least one layer of second insulating material is interposed between adjacent subsections.
    Type: Application
    Filed: June 26, 2013
    Publication date: March 6, 2014
    Inventors: Michael Noel Morrissey, Jan Kubik, Shane Patrick Geary, Patrick Martin McGuinness, Catriona Marie O'Sullivan