Patents by Inventor Shang-Bin Ko

Shang-Bin Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SRAM cell having a rectangular combined active area planar pass gate and planar pull-down NFETS
    Patent number: 8088663
    Abstract: A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: January 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Xiangdong Chen, Shang-Bin Ko, Dae-Gyu Park
  • SRAM CELL HAVING A RECTANGULAR COMBINED ACTIVE AREA FOR PLANAR PASS GATE AND PLANAR PULL-DOWN NFETS
    Publication number: 20110111584
    Abstract: A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means.
    Type: Application
    Filed: January 13, 2011
    Publication date: May 12, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiangdong Chen, Shang-Bin Ko, Dae-Gyu Park
  • SRAM cell having a rectangular combined active area for planar pass gate and planar pull-down NFETS
    Patent number: 7911008
    Abstract: A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: March 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Xiangdong Chen, Shang-Bin Ko, Dae-Gyu Park
  • SRAM CELL HAVING A RECTANGULAR COMBINED ACTIVE AREA FOR PLANAR PASS GATE AND PLANAR PULL-DOWN NFETS
    Publication number: 20090108372
    Abstract: A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means.
    Type: Application
    Filed: October 25, 2007
    Publication date: April 30, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiangdong Chen, Shang-Bin Ko, Dae-Gyu Park
  • Method of forming an oxide film on a gate side wall of a gate structure
    Patent number: 6605521
    Abstract: In order to prevent abnormal oxidation of the side wall of a polycide gate conductor layer in the oxidation heat treatment process after the RIE processing of the polycide gate conductor layer in a semiconductor memory cell, the heat treatment for oxidizing the side wall of the polycide gate conductor layer is conducted in two steps with different conditions. By conducting the first heat treatment process in an inert atmosphere, a thin oxide film is formed on the side wall of the polycide tungsten/gate conductor layer. Then by conducting the second heat treatment process in an atmosphere with a strong oxidizing property, a thick oxide film without abnormal oxidation can be formed.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: August 12, 2003
    Assignees: Kabushiki Kaisha Toshiba, International Business Machines Corporation
    Inventors: Atul C. Ajmera, Karanam Balasubramanyam, Tomio Katata, Shang-Bin Ko
  • Method of forming an oxide film on a gate side wall of a gate structure
    Publication number: 20030036253
    Abstract: In order to prevent abnormal oxidation of the side wall of a polycide gate conductor layer in the oxidation heat treatment process after the RIE processing of the polycide gate conductor layer in a semiconductor memory cell, the heat treatment for oxidizing the side wall of the polycide gate conductor layer is conducted in two steps with different conditions. By conducting the first heat treatment process in an inert atmosphere, a thin oxide film is formed on the side wall of the polycide tungsten/gate conductor layer. Then by conducting the second heat treatment process in an atmosphere with a strong oxidizing property, a thick oxide film without abnormal oxidation can be formed.
    Type: Application
    Filed: October 8, 2002
    Publication date: February 20, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atul C. Ajmera, Karanam Balasubramanyam, Tomio Katata, Shang-Bin Ko