Abstract: An electronic circuit includes: a data input port, a timing adjustment circuit configured to receive data from the data input port, first and second logic circuits, a multiplexer, and a data output port. The timing adjustment circuit includes two paths configured to impose first and second delays to generate first and second delayed data. The first and second logic circuits are configured to respectively receive the first and second delayed data and generate first and second logic outputs. The first logic output expands a pulse width corresponding to a first logic value. The second logic output expands a pulse width corresponding to a second logic value. The multiplexer is configured to select, based on an equalization feedback, at least one of the first logic output or the second logic output, to provide the multiplexer output. The data output port is configured to output equalized data based on the multiplexer output.

Abstract: A differential amplifier includes an input pair of transistors with a source-side resistor circuit, having a transistor biased in a triode region, and a current source. The resistor circuit in combination with a capacitance, causes source degeneration in the amplifier. The source side resistor circuit includes a first MOS transistor having a first channel terminal connected to the source of a first transistor in the differential pair, and a second channel terminal connected to the bulk terminal, and a second MOS transistor having a first channel terminal connected to the source of a second transistor in the differential pair, and a second channel terminal connected to the bulk terminal. A bias circuit biases the first MOS transistor and the second MOS transistor in a triode region. The resistance of the source-side resistor circuit and the gain of the transistors in the differential amplifier can track across process corners.

Abstract: Systems, devices, methods, and circuits for managing reference currents in semiconductor devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in sets of memory cells and circuitry coupled to the memory cell array. Each set of one or more sets of memory cells in the memory cell array is associated with a respective reference current, and memory cells in sets associated with different reference currents have different threshold voltage distributions. The circuitry is configured to: determine information associated with a reference current for a set of memory cells in the memory cell array based on a memory address corresponding to the set, generate the reference current based on the information associated with the reference current for the set, and sense one or more memory cells in the set based on the reference current.

Abstract: Electronic circuits, memory devices, and methods for compensating for data distortion from channel loss are provided. In one aspect, an electronic circuit includes a converter circuit configured to convert an input signal to a digital signal and a compensation circuit coupled to the converter circuit. The converter circuit includes a sampling circuit configured to receive the digital signal and generate an output signal. The output signal includes a stream of bits to be transmitted at a plurality of consecutive clock cycles. The converter circuit also includes one or more equalizing circuits coupled to the sampling circuit. Each equalizing circuit is configured to receive a bit of an output feedback signal at one of the consecutive clock cycles. The sampling circuit is configured to generate the output signal based on the digital signal and a sum of one or more equalization outputs of the one or more equalizing circuits.

Abstract: A receiver circuit has a first stage circuit having a first stage input and a first stage output, the first stage output setting a first stage common mode voltage; a second stage circuit having a second stage input connected to the first stage output, and a second stage output setting a second stage common mode voltage; and a buffer circuit having a trip point voltage, connected to the second stage output. The first stage circuit can include circuit elements configured to establish the first stage common mode voltage so that the second stage common mode voltage matches the trip point voltage. The second stage circuit can include a self-biased amplifier.

Abstract: A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

Abstract: A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.

Abstract: A continuous time linear equalizer (CTLE) circuit is provided. The CTLE circuit can include a differential pair of first and second transistors, the first and second transistors having drains connected through first and second drain resistors to a drain-side supply voltage node, and sources connected together by a source resistor and connected to one or more current sources, the first transistor in the differential pair having a gate connected to a reference voltage, and the second transistor in the differential pair having a gate connected to an input voltage, the drains of the first and second transistors providing a differential pair of signals as an output voltage, a first coupling capacitor connected between the source of the first transistor and the input voltage, and a second coupling capacitor connected to the source of the second transistor.

Abstract: A continuous time linear equalizer (CTLE) circuit is provided. The CTLE circuit can include a differential pair of first and second transistors, the first and second transistors having drains connected through first and second drain resistors to a drain-side supply voltage node, and sources connected together by a source resistor and connected to one or more current sources, the first transistor in the differential pair having a gate connected to a reference voltage, and the second transistor in the differential pair having a gate connected to an input voltage, the drains of the first and second transistors providing a differential pair of signals as an output voltage, a first coupling capacitor connected between the source of the first transistor and the input voltage, and a second coupling capacitor connected to the source of the second transistor.

Abstract: Compute-in-memory CIM operations using signed bits produce signed outputs. A circuit for CIM operations comprises an array of memory cells arranged in columns and rows, memory cells in columns connected to corresponding bit lines, and memory cells in rows connected to corresponding word lines. The array is programmable to store signed weights in sets of memory cells, the sets being operatively coupled with a corresponding pair of bit lines and a corresponding pair of word lines. Word line drivers are configured to drive true and complement voltages representing signed inputs on respective word lines in selected pairs of word lines. Sensing circuits are configured to sense differences between first and second currents on respective bit lines in selected pairs of bit lines and to produce signed outputs for the selected pairs of bit lines as a function of the difference.

Abstract: Systems, devices, methods, and circuits for managing reference currents in semiconductor devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in sets of memory cells and circuitry coupled to the memory cell array. Each set of one or more sets of memory cells in the memory cell array is associated with a respective reference current, and memory cells in sets associated with different reference currents have different threshold voltage distributions. The circuitry is configured to: determine information associated with a reference current for a set of memory cells in the memory cell array based on a memory address corresponding to the set, generate the reference current based on the information associated with the reference current for the set, and sense one or more memory cells in the set based on the reference current.

Abstract: A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.

Abstract: Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect, an integrated circuit includes: a latch circuit including a latch and a sensing transistor coupled to the latch, and a compensation circuit coupled to the sensing transistor. The sensing transistor includes a gate terminal coupled to a sensing node and an additional terminal coupled to the compensation circuit, and the compensation circuit is configured to apply a control voltage to the additional terminal to compensate for a variation of a threshold voltage of the sensing transistor.

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, memory cell lines connecting respective lines of memory cells, and a page buffer circuit including page buffers coupled to the memory cell lines. Each page buffer includes a sensing latch circuit and a storage latch circuit. The sensing latch circuit includes a sensing transistor coupled to a sensing node and at least one sensing latch unit having a first node coupled to the sensing node and a second node coupled to a first terminal of the sensing transistor. The storage latch circuit includes at least one storage latch unit having third and fourth nodes coupled to the sensing node and a gate terminal of the sensing transistor. A second terminal of the sensing transistor is coupled to a ground.

Abstract: A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

Abstract: Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect of this disclosure, an integrated circuit includes: a latch circuit including a latch and a sensing transistor coupled to the latch, and a compensation circuit coupled to the sensing transistor. The sensing transistor includes a gate terminal coupled to a sensing node and an additional terminal coupled to the compensation circuit, and the compensation circuit is configured to apply a control voltage to the additional terminal to compensate for a variation of a threshold voltage of the sensing transistor.

Abstract: Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing reference voltages, e.g., with current compensation, in memory systems, e.g., non-volatile memory systems. In one aspect, an integrated circuit includes: an operational amplifier configured to receive input voltages and a supply voltage and output a control voltage based on the input voltages and the supply voltage; an output circuitry configured to receive the control voltage from the operational amplifier and the supply voltage, provide the input voltages to the operational amplifier, and output a reference voltage; and a compensation circuitry coupled to the output circuitry and configured to output a compensation current to compensate the output circuitry such that the reference voltage is substantially constant. The output circuitry is configured to generate the reference voltage based on the control voltage and the compensation current.

Abstract: A sense amplifying device includes a bit line bias voltage adjuster and a sense amplifying circuit. The bit line bias voltage adjuster receives a power voltage to be an operation voltage. The bit line bias voltage adjuster includes a first amplifier, a first transistor and a first current source. The first amplifier, based on the power voltage, generates an adjusted reference bit line voltage according to a reference bit line voltage and a feedback voltage. The first transistor receives the adjusted reference bit line voltage and generates the feedback voltage, wherein the first transistor is a native transistor. The sense amplifying circuit receives the power voltage to be the operation voltage, and generates a sensing result according to the adjusted reference bit line voltage.

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, memory cell lines connecting respective lines of memory cells, and a page buffer circuit including page buffers coupled to the memory cell lines. Each page buffer includes a sensing latch circuit and a storage latch circuit. The sensing latch circuit includes a sensing transistor coupled to a sensing node and at least one sensing latch unit having a first node coupled to the sensing node and a second node coupled to a first terminal of the sensing transistor. The storage latch circuit includes at least one storage latch unit having third and fourth nodes coupled to the sensing node and a gate terminal of the sensing transistor. A second terminal of the sensing transistor is coupled to a ground.

Abstract: A sense amplifying device includes a bit line bias voltage adjuster and a sense amplifying circuit. The bit line bias voltage adjuster receives a power voltage to be an operation voltage. The bit line bias voltage adjuster includes a first amplifier, a first transistor and a first current source. The first amplifier, based on the power voltage, generates an adjusted reference bit line voltage according to a reference bit line voltage and a feedback voltage. The first transistor receives the adjusted reference bit line voltage and generates the feedback voltage, wherein the first transistor is a native transistor. The sense amplifying circuit receives the power voltage to be the operation voltage, and generates a sensing result according to the adjusted reference bit line voltage.