Abstract: A memory circuit includes a memory cell, a data line configured to be coupled with the memory cell, a node, a precharge circuit, a first transistor of a first type, and a second transistor of the first type. The precharge circuit is configured to charge the node toward a predetermined voltage level. The first transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the first transistor has a first threshold voltage. The second transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the second transistor having a second threshold voltage different from the first threshold voltage.

Abstract: An electronic device includes a first circuit, and a delay circuit electrically connected to the first circuit. The delay circuit includes a resistor, a capacitor, and a process, voltage or temperature (PVT) compensation circuit electrically connected to the capacitor.

Abstract: A memory circuit includes a memory cell, a data line configured to be coupled with the memory cell, a node, a precharge circuit, a first transistor of a first type, and a second transistor of the first type. The precharge circuit is configured to charge the node toward a predetermined voltage level. The first transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the first transistor has a first threshold voltage. The second transistor of the first type has a drain coupled with the node and a source coupled with the data line, and the second transistor having a second threshold voltage different from the first threshold voltage.

Abstract: An electronic device includes a first circuit, and a delay circuit electrically connected to the first circuit. The delay circuit includes a resistor, a capacitor, and a process, voltage or temperature (PVT) compensation circuit electrically connected to the capacitor.

Abstract: A memory circuit includes a memory cell, a data line coupled to the memory cell, a sense amplifier having an input terminal, a precharge circuit coupled to the input terminal of the sense amplifier, a first transistor of a first type, and a second transistor of the first type. The first transistor is coupled between the input terminal of the sense amplifier and the data line, and the second transistor is coupled between to the input terminal of the sense amplifier and the data line. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage lower than the first threshold voltage.

Abstract: In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page.

Abstract: In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page.

Abstract: A memory circuit includes a memory cell, a data line coupled to the memory cell, a sense amplifier having an input terminal, a precharge circuit coupled to the input terminal of the sense amplifier, a first transistor of a first type, and a second transistor of the first type. The first transistor is coupled between the input terminal of the sense amplifier and the data line, and the second transistor is coupled between to the input terminal of the sense amplifier and the data line. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage lower than the first threshold voltage.

Abstract: A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays.

Abstract: A sense amplifier circuit includes a precharge circuit configured to precharge a bit line coupled to a sensing node in response to a precharge control signal and a sense output circuit. The sense output circuit includes a sense output inverter coupled to the sensing node. The sense output inverter is disabled during bit line precharging and for a period after bit line precharging is complete, and thereafter the sense output inverter is enabled.

Abstract: A memory circuit includes a group of memory arrays and at least one redundancy bit line. The group of memory arrays includes a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. The at least one redundancy bit line is configured to selectively repair the group of memory arrays.

Abstract: A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third IO interface and a fourth memory array coupled with a fourth TO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.

Abstract: A sense amplifier circuit includes a precharge circuit configured to precharge a bit line coupled to a sensing node in response to a precharge control signal and a sense output circuit. The sense output circuit includes a sense output inverter coupled to the sensing node. The sense output inverter is disabled during bit line precharging and for a period after bit line precharging is complete, and thereafter the sense output inverter is enabled.

Abstract: A memory circuit includes a first group of memory arrays including a first memory array coupled with a first input/output (IO) interface and a second memory array coupled with a second IO interface. A second group of memory arrays include a third memory array coupled with a third input/output (IO) interface and a fourth memory array coupled with a fourth IO interface. A plurality of redundancy bit lines include at least one first redundancy bit line that is configured for selectively repairing the first group of memory arrays, and at least one second redundancy bit line that is configured for selectively repairing the second group of memory arrays.

Abstract: A method and system is disclosed for prohibiting program disturbance in a memory array device. The system comprises a bit-line decoder coupled to each bit-line of the memory array for providing a predetermined current diverting path, a biased resistance module placed on the bit-line of the flash memory array through which a pull-up current provided by a predetermined power supply is diverted by the bit-line decoder when a cell of the flash memory array connecting to the bit-line is programmed. The programming current of the cell of the flash memory array is stabilized due to the diverted pull-up current.

Abstract: A method and system for preventing white pixel difficulties resulting from undesired current induced in an image sensor having a photodiode and a depletion region therein. The photodiode is isolated in a pixel layout for an image sensor. A depletion region is configured, such that the depletion region is maintained in a defect-free region associated with the pixel layout for the image sensor, thereby reducing white pixel difficulties caused by induced and undesired current. The image sensor is preferably a CMOS image sensor. A depletion region of the photodiode is constantly maintained in a defect-free region during operation of the CMOS image sensor.

Abstract: A method and system is disclosed for prohibiting program disturbance in a memory array device. The system comprises a bit-line decoder coupled to each bit-line of the memory array for providing a predetermined current diverting path, a biased resistance module placed on the bit-line of the flash memory array through which a pull-up current provided by a predetermined power supply is diverted by the bit-line decoder when a cell of the flash memory array connecting to the bit-line is programmed. The programming current of the cell of the flash memory array is stabilized due to the diverted pull-up current.

Abstract: A method and system for preventing white pixel difficulties resulting from undesired current induced in an image sensor having a photodiode and a depletion region therein. The photodiode is isolated in a pixel layout for an image sensor. A depletion region is configured, such that the depletion region is maintained in a defect-free region associated with the pixel layout for the image sensor, thereby reducing white pixel difficulties caused by induced and undesired current. The image sensor is preferably a CMOS image sensor. A depletion region of the photodiode is constantly maintained in a defect-free region during operation of the CMOS image sensor.