Abstract: A transistor device comprising a semiconductor substrate composition a first gate electrode material disposed over a portion of a surface of the substrate composition wherein the first gate electrode material includes a first gate electrode contact region near at least one edge of the substrate composition. A gate insulating material is located over the first gate electrode material including two or more first gate vias through the gate insulating material in the first gate electrode contact region wherein the two or more first gate vias expose the first gate electrode material. A transistor device package includes a gate controller integrated circuit including a first transistor gate driver output node. A first gate conductive redistribution material connects the first gate electrode material of the first transistor device to the output node of the gate controller integrated circuit through the two or more first gate vias.

Abstract: In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spaced apart filled trenches having doped regions of opposite or alternating conductivity types surrounding the trenches.

Abstract: In one embodiment, a high voltage semiconductor device is formed with a first dielectric layer and a charge stabilization layer comprising a flowable glass formed over the first dielectric layer.

Abstract: In one embodiment, a lateral FET structure (30) is formed in a body of semiconductor material (32). The structure (30) includes a plurality non-interdigitated drain regions (39) that are coupled together with a conductive layer (57), and a plurality of source regions (34) that are coupled together with a different conductive layer (51). One or more interlayer dielectrics (53,54) separate the two conductive layers (51,57). The individual source regions (34) are absent small radius fingertip regions.

Abstract: In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The body of semiconductor material includes alternating layers of opposite conductivity type that extend between a trench drain region and a trench gate structure. The trench gate structure controls at least one sub-surface channel region. The body of semiconductor material provides sub-surface drift regions to reduce on resistance without increasing device area.

Abstract: In one embodiment, a lateral FET structure (30) is formed in a body of semiconductor material (32). The structure (30) includes a plurality non-interdigitated drain regions (39) that are coupled together with a conductive layer (57), and a plurality of source regions (34) that are coupled together with a different conductive layer (51). One or more interlayer dielectrics (53,54) separate the two conductive layers (51,57). The individual source regions (34) are absent small radius fingertip regions.