Patents by Inventor Shang-Liang Chen

Shang-Liang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11937932
    Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.
    Type: Grant
    Filed: July 8, 2022
    Date of Patent: March 26, 2024
    Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITY
    Inventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
  • Patent number: 11942420
    Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
  • Publication number: 20240095433
    Abstract: An integrated circuit includes a first conductor segment intersecting a first active-region structure at a source/drain region and a second conductor segment intersecting a second active-region structure at a source/drain region. The first conductor segment and the second conductor segment are separated at proximal edges by a separation distance. A distance from a first horizontal cell boundary to a proximal edge of the first conductor segment is larger than a distance from a second horizontal cell boundary to a proximal edge of the second conductor segment by a predetermined distance that is a fraction of the separation distance.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Hsuan CHIU
  • Publication number: 20240096756
    Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
  • Publication number: 20240086611
    Abstract: Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Hsuan Chiu, Chih-Liang Chen, Hui-Zhong Zhuang, Chi-Yu Lu, Kuang-Ching Chang
  • Patent number: 6398418
    Abstract: A shaft having thermal expansion, thermal pre-load yielding and dynamic pre-load adjusting systems. The shaft is made by the zero expansion or very low expansion materials. The shaft has two bearing assemblies. Each bearing assembly has two parallel bearings. A partition ring set is disposed between them. The partition ring set is made of multiple low and negative thermal expansion materials. It includes an inner partition ring and an outer partition ring. The inner partition ring is tightly contacting with corresponding sides of inner annular seats of the bearing. The outer partition ring is disposed outside of the inner partition ring without any contact. And, the outer partition ring is tightly contacting with corresponding sides of outer annular seats of the bearings.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: June 4, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Tsann-Huei Chang, Jih-Jong Hsu, Shang-Liang Chen
  • Patent number: 6048143
    Abstract: A composite mechanism multi-axis machine tool includes an orthogonal coordinate feeding axis mechanism and a parallel type spatial linkage mechanism. The orthogonal coordinate feeding axis mechanism has two orthogonal platforms to provide two dimensional motion vectors. The parallel type spatial linkage mechanism has three sets of linear feeding modules engaging with a base frame for holding a main spindle which further holds a tool cutter. The parallel type spatial linkage mechanism provides one dimensional motion and two dimensional rotation for the tool cutter. A controller is provided to control and coordinate the movements of the orthogonal coordinate feeding axis mechanism and the parallel type spatial linkage mechanism.
    Type: Grant
    Filed: January 30, 1999
    Date of Patent: April 11, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Tsann-Huei Chang, Yeou-Bin Guu, Shang-Liang Chen