Abstract: An active device substrate includes a substrate, a first thin film transistor located above the substrate and a second thin film transistor located above the substrate. The first thin film transistor includes a first metal oxide layer, a first gate, a first source and a first drain. A first gate dielectric layer and a second gate dielectric layer are located between the first gate and the first metal oxide layer. The second thin film transistor includes a second metal oxide layer, a second gate, a second source and a second drain. The second gate dielectric layer is located between the second gate and the second metal oxide layer, and the second metal oxide layer is located between the first gate dielectric layer and the second gate dielectric layer. The first gate and the second gate belong to a same patterned layer.

Abstract: A memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns. Each of the plurality of voltage control circuits includes a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column. The first voltage drop is substantially smaller than the second voltage drop.

Abstract: A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: An integrated circuit device includes a first transistor having a first-type channel and a second transistor having a second-type channel at a front side of a substrate. The first transistor is stacked over the second transistor. The integrated circuit device also includes a power line connected to a source terminal of the first transistor. The first transistor has a gate terminal configured to receive a control signal and has a drain terminal connected to both a gate terminal and a drain terminal of the second transistor. The integrated circuit device further includes a memory power line connected to a source terminal of the second transistor and a memory circuit configured to receive a supply voltage from the memory power line.

Abstract: An integrated circuit (IC) device includes a plurality of memory segments. Each memory segment includes a plurality of memory cells, and a local bit line electrically coupled to the plurality of memory cells and arranged on a first side of the IC device. The IC device further includes a global bit line electrically coupled to the plurality of memory segments, and arranged on a second side of the IC device. The second side is opposite the first side in a thickness direction of the IC device.

Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a substrate, a first silicon nitride (SiN) layer, a second SiN layer, an oxide insulation layer, and a first metal oxide layer. The first SiN layer is located on or above the substrate. The second SiN layer is located above the first SiN layer. Both the first SiN layer and the second SiN layer include a hydrogen element. The second SiN layer has a hydrogen concentration lower than that of the first SiN layer and a thickness less than that of the first SiN layer. The oxide insulation layer is located on the second SiN layer. The first metal oxide layer is located on the oxide insulation layer. The second SiN layer is located between the first metal oxide layer and the substrate.

Abstract: An active device substrate includes a substrate, a first thin film transistor located above the substrate and a second thin film transistor located above the substrate. The first thin film transistor includes a first metal oxide layer, a first gate, a first source and a first drain. A first gate dielectric layer and a second gate dielectric layer are located between the first gate and the first metal oxide layer. The second thin film transistor includes a second metal oxide layer, a second gate, a second source and a second drain. The second gate dielectric layer is located between the second gate and the second metal oxide layer, and the second metal oxide layer is located between the first gate dielectric layer and the second gate dielectric layer. The first gate and the second gate belong to a same patterned layer.

Abstract: According to at least one aspect of the present disclosure, a method of operating a, Uninterruptible Power Supply (UPS) is provided. The method includes receiving, in a first mode of operation, AC power at an input of the UPS, providing, in the first mode, the AC power to a charger and a clamp-charger circuit, charging, by the charger in the first mode, a UPS battery of the UPS with a first charging current derived from at least a portion of the AC power, charging, by the clamp-charger circuit in the first mode, the UPS battery with a second charging current derived from at least a portion of the AC power, providing, in a second mode of operation, output power at an output of the UPS derived from the UPS battery, and charging, by the clamp-charger circuit in the second mode, the UPS battery using a third charging current.

Abstract: According to at least one aspect of the present disclosure, a method of operating a, Uninterruptible Power Supply (UPS) is provided. The method includes receiving, in a first mode of operation, AC power at an input of the UPS, providing, in the first mode, the AC power to a charger and a clamp-charger circuit, charging, by the charger in the first mode, a UPS battery of the UPS with a first charging current derived from at least a portion of the AC power, charging, by the clamp-charger circuit in the first mode, the UPS battery with a second charging current derived from at least a portion of the AC power, providing, in a second mode of operation, output power at an output of the UPS derived from the UPS battery, and charging, by the clamp-charger circuit in the second mode, the UPS battery using a third charging current.