Abstract: The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.

Abstract: The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.

Abstract: A packet processing accelerator comprises a programmable packet classification module, a programmable flow control module, and a programmable packet header modification module. The programmable packet classification module is configured to receive a data packet and generate a start location of each protocol header of the data packet and a first index. The first index indicates classification of the data packet. The programmable flow control module is configured to generate a code of an output port and an action code according to the start location of each protocol header of the data packet and the first index. The programmable packet header modification module is configured to modify content of a plurality of protocol headers of the data packet according to the action code and to send the modified data packet to an output port according to the code of the output port.

Abstract: A measurement data recording system includes a microprocessor, a first switch and a second switch. The first switch sends a trigger signal to trigger a digital measurement instrument sends a measurement data. The microprocessor detects the trigger signal aroused by the first switch, receives the measurement data, and records it into the memory card. The microprocessor also detects a trigger signal aroused by the second switch and deletes the measurement data in the memory card. A method for recording the measurement data includes steps of detecting the trigger signal, detecting a status of the memory card, detecting a status of a data file in the memory card, receiving the measurement data and recording it into the data file while the trigger signal being aroused by the first switch, and deleting the measurement data recorded in the data file while the trigger signal being aroused by the second switch.

Abstract: A system and method for voice quality analysis include the ability to receive packets in a voice stream and to generate a receipt indicator for the packets. The system and method also include the ability to substitute a reference voice sample for the voice data in the packets and to compare the voice data in the voice-substituted packets to the reference voice sample to determine voice quality.